a8251.fit.qmsg

8251芯片功能的vhdl描述

{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nRxC Global clock in PIN R25 " "Info: Automatically promoted signal \"nRxC\" to use Global clock in PIN R25" {  } { { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 46 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "clk Global clock in PIN R27 " "Info: Automatically promoted signal \"clk\" to use Global clock in PIN R27" {  } { { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 36 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "nTxC Global clock in PIN P25 " "Info: Automatically promoted signal \"nTxC\" to use Global clock in PIN P25" {  } { { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 45 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "proc:i_procintf\|proc_dec:I_proc_dec\|decode~52 Global clock " "Info: Automatically promoted some destinations of signal \"proc:i_procintf\|proc_dec:I_proc_dec\|decode~52\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "Wr_Ext:i_Wr_Ext\|WriteExtProc~28 " "Info: Destination \"Wr_Ext:i_Wr_Ext\|WriteExtProc~28\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "proc:i_procintf\|proc_dec:I_proc_dec\|decode~52" } } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { proc:i_procintf|proc_dec:I_proc_dec|decode~52 } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { proc:i_procintf|proc_dec:I_proc_dec|decode~52 } "NODE_NAME" } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "proc:i_procintf\|proc_dec:I_proc_dec\|decode~53 Global clock " "Info: Automatically promoted signal \"proc:i_procintf\|proc_dec:I_proc_dec\|decode~53\" to use Global clock" {  } { { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "proc:i_procintf\|proc_dec:I_proc_dec\|decode~53" } } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { proc:i_procintf|proc_dec:I_proc_dec|decode~53 } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { proc:i_procintf|proc_dec:I_proc_dec|decode~53 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reset Global clock in PIN P27 " "Info: Automatically promoted some destinations of signal \"reset\" to use Global clock in PIN P27" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_data_cnt:i_tx_data_cnt\|data_tc~40 " "Info: Destination \"tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_data_cnt:i_tx_data_cnt\|data_tc~40\" may be non-global or may not use global clock" {  } { { "Tx_data_cnt.vhd" "" { Text "G:/design/summer work/download/8251/Tx_data_cnt.vhd" 55 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|Equal0~705 " "Info: Destination \"rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|Equal0~705\" may be non-global or may not use global clock" {  } { { "d:/altera1/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera1/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|Equal0~706 " "Info: Destination \"rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|Equal0~706\" may be non-global or may not use global clock" {  } { { "d:/altera1/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera1/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|Mux9~142 " "Info: Destination \"rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|Mux9~142\" may be non-global or may not use global clock" {  } { { "Rx_break_cnt.vhd" "" { Text "G:/design/summer work/download/8251/Rx_break_cnt.vhd" 114 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|Equal0~707 " "Info: Destination \"rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|Equal0~707\" may be non-global or may not use global clock" {  } { { "d:/altera1/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera1/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|Equal0~708 " "Info: Destination \"rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|Equal0~708\" may be non-global or may not use global clock" {  } { { "d:/altera1/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera1/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|Equal0~709 " "Info: Destination \"rx:i_rx\|rx_break_cnt:i_rx_break_cnt\|Equal0~709\" may be non-global or may not use global clock" {  } { { "d:/altera1/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera1/quartus6.0/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|Selector3~432 " "Info: Destination \"tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|Selector3~432\" may be non-global or may not use global clock" {  } { { "Tx_state_mach.vhd" "" { Text "G:/design/summer work/download/8251/Tx_state_mach.vhd" 168 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|Selector3~434 " "Info: Destination \"tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|Selector3~434\" may be non-global or may not use global clock" {  } { { "Tx_state_mach.vhd" "" { Text "G:/design/summer work/download/8251/Tx_state_mach.vhd" 168 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|Selector3~436 " "Info: Destination \"tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|Selector3~436\" may be non-global or may not use global clock" {  } { { "Tx_state_mach.vhd" "" { Text "G:/design/summer work/download/8251/Tx_state_mach.vhd" 168 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 37 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "tx_fifo:i_tx_fifo\|ff_wr_proc~21 Global clock " "Info: Automatically promoted signal \"tx_fifo:i_tx_fifo\|ff_wr_proc~21\" to use Global clock" {  } { { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "tx_fifo:i_tx_fifo\|ff_wr_proc~21" } } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { tx_fifo:i_tx_fifo|ff_wr_proc~21 } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { tx_fifo:i_tx_fifo|ff_wr_proc~21 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}