a8251.map.qmsg

8251芯片功能的vhdl描述

{ "Info" "ISGN_START_ELABORATION_TOP" "A8251 " "Info: Elaborating entity \"A8251\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dout_mux dout_mux:i_dout_mux " "Info: Elaborating entity \"dout_mux\" for hierarchy \"dout_mux:i_dout_mux\"" {  } { { "A8251.vhd" "i_dout_mux" { Text "G:/design/summer work/download/8251/A8251.vhd" 341 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DataLatch DataLatch:i_DataSync " "Info: Elaborating entity \"DataLatch\" for hierarchy \"DataLatch:i_DataSync\"" {  } { { "A8251.vhd" "i_DataSync" { Text "G:/design/summer work/download/8251/A8251.vhd" 350 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "LatchedData data_latch.vhd(59) " "Warning (10631): VHDL Process Statement warning at data_latch.vhd(59): inferring latch(es) for signal or variable \"LatchedData\", which holds its previous value in one or more paths through the process" {  } { { "data_latch.vhd" "" { Text "G:/design/summer work/download/8251/data_latch.vhd" 59 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LatchedData\[0\] data_latch.vhd(59) " "Info (10041): Verilog HDL or VHDL info at data_latch.vhd(59): inferred latch for \"LatchedData\[0\]\"" {  } { { "data_latch.vhd" "" { Text "G:/design/summer work/download/8251/data_latch.vhd" 59 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LatchedData\[1\] data_latch.vhd(59) " "Info (10041): Verilog HDL or VHDL info at data_latch.vhd(59): inferred latch for \"LatchedData\[1\]\"" {  } { { "data_latch.vhd" "" { Text "G:/design/summer work/download/8251/data_latch.vhd" 59 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LatchedData\[2\] data_latch.vhd(59) " "Info (10041): Verilog HDL or VHDL info at data_latch.vhd(59): inferred latch for \"LatchedData\[2\]\"" {  } { { "data_latch.vhd" "" { Text "G:/design/summer work/download/8251/data_latch.vhd" 59 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LatchedData\[3\] data_latch.vhd(59) " "Info (10041): Verilog HDL or VHDL info at data_latch.vhd(59): inferred latch for \"LatchedData\[3\]\"" {  } { { "data_latch.vhd" "" { Text "G:/design/summer work/download/8251/data_latch.vhd" 59 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LatchedData\[4\] data_latch.vhd(59) " "Info (10041): Verilog HDL or VHDL info at data_latch.vhd(59): inferred latch for \"LatchedData\[4\]\"" {  } { { "data_latch.vhd" "" { Text "G:/design/summer work/download/8251/data_latch.vhd" 59 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LatchedData\[5\] data_latch.vhd(59) " "Info (10041): Verilog HDL or VHDL info at data_latch.vhd(59): inferred latch for \"LatchedData\[5\]\"" {  } { { "data_latch.vhd" "" { Text "G:/design/summer work/download/8251/data_latch.vhd" 59 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LatchedData\[6\] data_latch.vhd(59) " "Info (10041): Verilog HDL or VHDL info at data_latch.vhd(59): inferred latch for \"LatchedData\[6\]\"" {  } { { "data_latch.vhd" "" { Text "G:/design/summer work/download/8251/data_latch.vhd" 59 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LatchedData\[7\] data_latch.vhd(59) " "Info (10041): Verilog HDL or VHDL info at data_latch.vhd(59): inferred latch for \"LatchedData\[7\]\"" {  } { { "data_latch.vhd" "" { Text "G:/design/summer work/download/8251/data_latch.vhd" 59 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AddrLatch AddrLatch:i_AddrSync " "Info: Elaborating entity \"AddrLatch\" for hierarchy \"AddrLatch:i_AddrSync\"" {  } { { "A8251.vhd" "i_AddrSync" { Text "G:/design/summer work/download/8251/A8251.vhd" 360 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "LatchedAddr addr_latch.vhd(63) " "Warning (10631): VHDL Process Statement warning at addr_latch.vhd(63): inferring latch(es) for signal or variable \"LatchedAddr\", which holds its previous value in one or more paths through the process" {  } { { "addr_latch.vhd" "" { Text "G:/design/summer work/download/8251/addr_latch.vhd" 63 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "LatchedAddr addr_latch.vhd(63) " "Info (10041): Verilog HDL or VHDL info at addr_latch.vhd(63): inferred latch for \"LatchedAddr\"" {  } { { "addr_latch.vhd" "" { Text "G:/design/summer work/download/8251/addr_latch.vhd" 63 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Wr_Ext Wr_Ext:i_Wr_Ext " "Info: Elaborating entity \"Wr_Ext\" for hierarchy \"Wr_Ext:i_Wr_Ext\"" {  } { { "A8251.vhd" "i_Wr_Ext" { Text "G:/design/summer work/download/8251/A8251.vhd" 370 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "proc proc:i_procintf " "Info: Elaborating entity \"proc\" for hierarchy \"proc:i_procintf\"" {  } { { "A8251.vhd" "i_procintf" { Text "G:/design/summer work/download/8251/A8251.vhd" 380 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "proc_cmd_reg proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg " "Info: Elaborating entity \"proc_cmd_reg\" for hierarchy \"proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\"" {  } { { "Proc.vhd" "I_proc_cmd_reg" { Text "G:/design/summer work/download/8251/Proc.vhd" 203 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "proc_mode_reg proc:i_procintf\|proc_mode_reg:I_proc_mode_reg " "Info: Elaborating entity \"proc_mode_reg\" for hierarchy \"proc:i_procintf\|proc_mode_reg:I_proc_mode_reg\"" {  } { { "Proc.vhd" "I_proc_mode_reg" { Text "G:/design/summer work/download/8251/Proc.vhd" 228 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "proc_dec proc:i_procintf\|proc_dec:I_proc_dec " "Info: Elaborating entity \"proc_dec\" for hierarchy \"proc:i_procintf\|proc_dec:I_proc_dec\"" {  } { { "Proc.vhd" "I_proc_dec" { Text "G:/design/summer work/download/8251/Proc.vhd" 242 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}