a8251.map.qmsg

8251芯片功能的vhdl描述

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 15 17:48:17 2007 " "Info: Processing started: Sun Jul 15 17:48:17 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off A8251 -c A8251 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off A8251 -c A8251" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "addr_latch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file addr_latch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 AddrLatch-rtl " "Info: Found design unit 1: AddrLatch-rtl" {  } { { "addr_latch.vhd" "" { Text "G:/design/summer work/download/8251/addr_latch.vhd" 57 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 AddrLatch " "Info: Found entity 1: AddrLatch" {  } { { "addr_latch.vhd" "" { Text "G:/design/summer work/download/8251/addr_latch.vhd" 38 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "data_latch.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file data_latch.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DataLatch-rtl " "Info: Found design unit 1: DataLatch-rtl" {  } { { "data_latch.vhd" "" { Text "G:/design/summer work/download/8251/data_latch.vhd" 56 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 DataLatch " "Info: Found entity 1: DataLatch" {  } { { "data_latch.vhd" "" { Text "G:/design/summer work/download/8251/data_latch.vhd" 38 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dout_mux.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file dout_mux.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 dout_mux-structure " "Info: Found design unit 1: dout_mux-structure" {  } { { "dout_mux.vhd" "" { Text "G:/design/summer work/download/8251/dout_mux.vhd" 50 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 dout_mux " "Info: Found entity 1: dout_mux" {  } { { "dout_mux.vhd" "" { Text "G:/design/summer work/download/8251/dout_mux.vhd" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Proc.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Proc.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 proc-structure " "Info: Found design unit 1: proc-structure" {  } { { "Proc.vhd" "" { Text "G:/design/summer work/download/8251/Proc.vhd" 78 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 proc " "Info: Found entity 1: proc" {  } { { "Proc.vhd" "" { Text "G:/design/summer work/download/8251/Proc.vhd" 37 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Proc_cmd_reg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Proc_cmd_reg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 proc_cmd_reg-rtl " "Info: Found design unit 1: proc_cmd_reg-rtl" {  } { { "Proc_cmd_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_cmd_reg.vhd" 66 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 proc_cmd_reg " "Info: Found entity 1: proc_cmd_reg" {  } { { "Proc_cmd_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_cmd_reg.vhd" 35 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PROC_DEC.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file PROC_DEC.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 proc_dec-rtl " "Info: Found design unit 1: proc_dec-rtl" {  } { { "PROC_DEC.VHD" "" { Text "G:/design/summer work/download/8251/PROC_DEC.VHD" 84 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 proc_dec " "Info: Found entity 1: proc_dec" {  } { { "PROC_DEC.VHD" "" { Text "G:/design/summer work/download/8251/PROC_DEC.VHD" 59 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Proc_mode_reg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Proc_mode_reg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 proc_mode_reg-rtl " "Info: Found design unit 1: proc_mode_reg-rtl" {  } { { "Proc_mode_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_mode_reg.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 proc_mode_reg " "Info: Found entity 1: proc_mode_reg" {  } { { "Proc_mode_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_mode_reg.vhd" 37 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Proc_sm.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Proc_sm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 proc_sm-rtl " "Info: Found design unit 1: proc_sm-rtl" {  } { { "Proc_sm.vhd" "" { Text "G:/design/summer work/download/8251/Proc_sm.vhd" 58 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 proc_sm " "Info: Found entity 1: proc_sm" {  } { { "Proc_sm.vhd" "" { Text "G:/design/summer work/download/8251/Proc_sm.vhd" 37 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Proc_sync_reg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Proc_sync_reg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 proc_sync_reg-rtl " "Info: Found design unit 1: proc_sync_reg-rtl" {  } { { "Proc_sync_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_sync_reg.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 proc_sync_reg " "Info: Found entity 1: proc_sync_reg" {  } { { "Proc_sync_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_sync_reg.vhd" 35 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Rx.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Rx.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx-struct " "Info: Found design unit 1: rx-struct" {  } { { "Rx.vhd" "" { Text "G:/design/summer work/download/8251/Rx.vhd" 71 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rx " "Info: Found entity 1: rx" {  } { { "Rx.vhd" "" { Text "G:/design/summer work/download/8251/Rx.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Rx_break_cnt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Rx_break_cnt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_break_cnt-rtl " "Info: Found design unit 1: rx_break_cnt-rtl" {  } { { "Rx_break_cnt.vhd" "" { Text "G:/design/summer work/download/8251/Rx_break_cnt.vhd" 71 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rx_break_cnt " "Info: Found entity 1: rx_break_cnt" {  } { { "Rx_break_cnt.vhd" "" { Text "G:/design/summer work/download/8251/Rx_break_cnt.vhd" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Rx_cntrl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Rx_cntrl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_cntrl-struct " "Info: Found design unit 1: rx_cntrl-struct" {  } { { "Rx_cntrl.vhd" "" { Text "G:/design/summer work/download/8251/Rx_cntrl.vhd" 63 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rx_cntrl " "Info: Found entity 1: rx_cntrl" {  } { { "Rx_cntrl.vhd" "" { Text "G:/design/summer work/download/8251/Rx_cntrl.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Rx_cntrl_cnt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Rx_cntrl_cnt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_cntrl_cnt-rtl " "Info: Found design unit 1: rx_cntrl_cnt-rtl" {  } { { "Rx_cntrl_cnt.vhd" "" { Text "G:/design/summer work/download/8251/Rx_cntrl_cnt.vhd" 51 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rx_cntrl_cnt " "Info: Found entity 1: rx_cntrl_cnt" {  } { { "Rx_cntrl_cnt.vhd" "" { Text "G:/design/summer work/download/8251/Rx_cntrl_cnt.vhd" 35 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Rx_cntrl_sm.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Rx_cntrl_sm.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_cntrl_sm-rtl " "Info: Found design unit 1: rx_cntrl_sm-rtl" {  } { { "Rx_cntrl_sm.vhd" "" { Text "G:/design/summer work/download/8251/Rx_cntrl_sm.vhd" 67 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rx_cntrl_sm " "Info: Found entity 1: rx_cntrl_sm" {  } { { "Rx_cntrl_sm.vhd" "" { Text "G:/design/summer work/download/8251/Rx_cntrl_sm.vhd" 32 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Rx_data_cnt.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Rx_data_cnt.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_data_cnt-rtl " "Info: Found design unit 1: rx_data_cnt-rtl" {  } { { "Rx_data_cnt.vhd" "" { Text "G:/design/summer work/download/8251/Rx_data_cnt.vhd" 57 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rx_data_cnt " "Info: Found entity 1: rx_data_cnt" {  } { { "Rx_data_cnt.vhd" "" { Text "G:/design/summer work/download/8251/Rx_data_cnt.vhd" 35 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Rx_data_reg.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Rx_data_reg.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_data_reg-rtl " "Info: Found design unit 1: rx_data_reg-rtl" {  } { { "Rx_data_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_data_reg.vhd" 53 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rx_data_reg " "Info: Found entity 1: rx_data_reg" {  } { { "Rx_data_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_data_reg.vhd" 33 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Rx_det_cntrl.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Rx_det_cntrl.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rx_det_cntrl-rtl " "Info: Found design unit 1: rx_det_cntrl-rtl" {  } { { "Rx_det_cntrl.vhd" "" { Text "G:/design/summer work/download/8251/Rx_det_cntrl.vhd" 57 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 rx_det_cntrl " "Info: Found entity 1: rx_det_cntrl" {  } { { "Rx_det_cntrl.vhd" "" { Text "G:/design/summer work/download/8251/Rx_det_cntrl.vhd" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}