a8251.tan.qmsg

8251芯片功能的vhdl描述

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "nRxC register rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|data\[5\] register rx:i_rx\|rx_data_cnt:i_rx_data_cnt\|int_dout\[2\] 148.54 MHz 6.732 ns Internal " "Info: Clock \"nRxC\" has Internal fmax of 148.54 MHz between source register \"rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|data\[5\]\" and destination register \"rx:i_rx\|rx_data_cnt:i_rx_data_cnt\|int_dout\[2\]\" (period= 6.732 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.548 ns + Longest register register " "Info: + Longest register to register delay is 6.548 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|data\[5\] 1 REG LC_X46_Y37_N5 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X46_Y37_N5; Fanout = 8; REG Node = 'rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|data\[5\]'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] } "NODE_NAME" } } { "Rx_shift_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_shift_reg.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.980 ns) + CELL(0.213 ns) 1.193 ns rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out\[5\]~4167 2 COMB LC_X43_Y37_N2 2 " "Info: 2: + IC(0.980 ns) + CELL(0.213 ns) = 1.193 ns; Loc. = LC_X43_Y37_N2; Fanout = 2; COMB Node = 'rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out\[5\]~4167'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.193 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4167 } "NODE_NAME" } } { "Rx_shift_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_shift_reg.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.087 ns) 1.419 ns rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out\[5\]~4168 3 COMB LC_X43_Y37_N3 1 " "Info: 3: + IC(0.139 ns) + CELL(0.087 ns) = 1.419 ns; Loc. = LC_X43_Y37_N3; Fanout = 1; COMB Node = 'rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out\[5\]~4168'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.226 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4167 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4168 } "NODE_NAME" } } { "Rx_shift_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_shift_reg.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.360 ns) + CELL(0.213 ns) 1.992 ns rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out\[5\]~4170 4 COMB LC_X43_Y37_N8 4 " "Info: 4: + IC(0.360 ns) + CELL(0.213 ns) = 1.992 ns; Loc. = LC_X43_Y37_N8; Fanout = 4; COMB Node = 'rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|par_out\[5\]~4170'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.573 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4168 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4170 } "NODE_NAME" } } { "Rx_shift_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_shift_reg.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.117 ns) + CELL(0.087 ns) 3.196 ns rx:i_rx\|rx_sync_comp:i_rx_sync_comp\|cmp_dat\[5\]~1720 5 COMB LC_X43_Y38_N9 2 " "Info: 5: + IC(1.117 ns) + CELL(0.087 ns) = 3.196 ns; Loc. = LC_X43_Y38_N9; Fanout = 2; COMB Node = 'rx:i_rx\|rx_sync_comp:i_rx_sync_comp\|cmp_dat\[5\]~1720'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.204 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4170 rx:i_rx|rx_sync_comp:i_rx_sync_comp|cmp_dat[5]~1720 } "NODE_NAME" } } { "Rx_sync_comp.vhd" "" { Text "G:/design/summer work/download/8251/Rx_sync_comp.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.332 ns) 3.864 ns rx:i_rx\|rx_sync_comp:i_rx_sync_comp\|Equal4~246 6 COMB LC_X43_Y38_N1 2 " "Info: 6: + IC(0.336 ns) + CELL(0.332 ns) = 3.864 ns; Loc. = LC_X43_Y38_N1; Fanout = 2; COMB Node = 'rx:i_rx\|rx_sync_comp:i_rx_sync_comp\|Equal4~246'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.668 ns" { rx:i_rx|rx_sync_comp:i_rx_sync_comp|cmp_dat[5]~1720 rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~246 } "NODE_NAME" } } { "Rx_sync_comp.vhd" "" { Text "G:/design/summer work/download/8251/Rx_sync_comp.vhd" 109 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.867 ns) + CELL(0.087 ns) 4.818 ns rx:i_rx\|rx_data_cnt:i_rx_data_cnt\|comb_proc~284 7 COMB LC_X47_Y38_N1 1 " "Info: 7: + IC(0.867 ns) + CELL(0.087 ns) = 4.818 ns; Loc. = LC_X47_Y38_N1; Fanout = 1; COMB Node = 'rx:i_rx\|rx_data_cnt:i_rx_data_cnt\|comb_proc~284'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.954 ns" { rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~246 rx:i_rx|rx_data_cnt:i_rx_data_cnt|comb_proc~284 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.369 ns) + CELL(0.213 ns) 5.400 ns rx:i_rx\|rx_data_cnt:i_rx_data_cnt\|comb_proc~287 8 COMB LC_X47_Y38_N4 4 " "Info: 8: + IC(0.369 ns) + CELL(0.213 ns) = 5.400 ns; Loc. = LC_X47_Y38_N4; Fanout = 4; COMB Node = 'rx:i_rx\|rx_data_cnt:i_rx_data_cnt\|comb_proc~287'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.582 ns" { rx:i_rx|rx_data_cnt:i_rx_data_cnt|comb_proc~284 rx:i_rx|rx_data_cnt:i_rx_data_cnt|comb_proc~287 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.782 ns) 6.548 ns rx:i_rx\|rx_data_cnt:i_rx_data_cnt\|int_dout\[2\] 9 REG LC_X47_Y38_N8 5 " "Info: 9: + IC(0.366 ns) + CELL(0.782 ns) = 6.548 ns; Loc. = LC_X47_Y38_N8; Fanout = 5; REG Node = 'rx:i_rx\|rx_data_cnt:i_rx_data_cnt\|int_dout\[2\]'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.148 ns" { rx:i_rx|rx_data_cnt:i_rx_data_cnt|comb_proc~287 rx:i_rx|rx_data_cnt:i_rx_data_cnt|int_dout[2] } "NODE_NAME" } } { "Rx_data_cnt.vhd" "" { Text "G:/design/summer work/download/8251/Rx_data_cnt.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.014 ns ( 30.76 % ) " "Info: Total cell delay = 2.014 ns ( 30.76 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.534 ns ( 69.24 % ) " "Info: Total interconnect delay = 4.534 ns ( 69.24 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "6.548 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4167 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4168 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4170 rx:i_rx|rx_sync_comp:i_rx_sync_comp|cmp_dat[5]~1720 rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~246 rx:i_rx|rx_data_cnt:i_rx_data_cnt|comb_proc~284 rx:i_rx|rx_data_cnt:i_rx_data_cnt|comb_proc~287 rx:i_rx|rx_data_cnt:i_rx_data_cnt|int_dout[2] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "6.548 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4167 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4168 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4170 rx:i_rx|rx_sync_comp:i_rx_sync_comp|cmp_dat[5]~1720 rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~246 rx:i_rx|rx_data_cnt:i_rx_data_cnt|comb_proc~284 rx:i_rx|rx_data_cnt:i_rx_data_cnt|comb_proc~287 rx:i_rx|rx_data_cnt:i_rx_data_cnt|int_dout[2] } { 0.000ns 0.980ns 0.139ns 0.360ns 1.117ns 0.336ns 0.867ns 0.369ns 0.366ns } { 0.000ns 0.213ns 0.087ns 0.213ns 0.087ns 0.332ns 0.087ns 0.213ns 0.782ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns - Smallest " "Info: - Smallest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "nRxC destination 3.234 ns + Shortest register " "Info: + Shortest clock path from clock \"nRxC\" to destination register is 3.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns nRxC 1 CLK PIN_R25 70 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R25; Fanout = 70; CLK Node = 'nRxC'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { nRxC } "NODE_NAME" } } { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.806 ns) + CELL(0.560 ns) 3.234 ns rx:i_rx\|rx_data_cnt:i_rx_data_cnt\|int_dout\[2\] 2 REG LC_X47_Y38_N8 5 " "Info: 2: + IC(1.806 ns) + CELL(0.560 ns) = 3.234 ns; Loc. = LC_X47_Y38_N8; Fanout = 5; REG Node = 'rx:i_rx\|rx_data_cnt:i_rx_data_cnt\|int_dout\[2\]'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.366 ns" { nRxC rx:i_rx|rx_data_cnt:i_rx_data_cnt|int_dout[2] } "NODE_NAME" } } { "Rx_data_cnt.vhd" "" { Text "G:/design/summer work/download/8251/Rx_data_cnt.vhd" 108 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.16 % ) " "Info: Total cell delay = 1.428 ns ( 44.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.806 ns ( 55.84 % ) " "Info: Total interconnect delay = 1.806 ns ( 55.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.234 ns" { nRxC rx:i_rx|rx_data_cnt:i_rx_data_cnt|int_dout[2] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.234 ns" { nRxC nRxC~out0 rx:i_rx|rx_data_cnt:i_rx_data_cnt|int_dout[2] } { 0.000ns 0.000ns 1.806ns } { 0.000ns 0.868ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "nRxC source 3.232 ns - Longest register " "Info: - Longest clock path from clock \"nRxC\" to source register is 3.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns nRxC 1 CLK PIN_R25 70 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R25; Fanout = 70; CLK Node = 'nRxC'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { nRxC } "NODE_NAME" } } { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 46 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.804 ns) + CELL(0.560 ns) 3.232 ns rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|data\[5\] 2 REG LC_X46_Y37_N5 8 " "Info: 2: + IC(1.804 ns) + CELL(0.560 ns) = 3.232 ns; Loc. = LC_X46_Y37_N5; Fanout = 8; REG Node = 'rx:i_rx\|rx_shift_reg:i_rx_shift_reg\|data\[5\]'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.364 ns" { nRxC rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] } "NODE_NAME" } } { "Rx_shift_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_shift_reg.vhd" 85 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.18 % ) " "Info: Total cell delay = 1.428 ns ( 44.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.804 ns ( 55.82 % ) " "Info: Total interconnect delay = 1.804 ns ( 55.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.232 ns" { nRxC rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.232 ns" { nRxC nRxC~out0 rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] } { 0.000ns 0.000ns 1.804ns } { 0.000ns 0.868ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.234 ns" { nRxC rx:i_rx|rx_data_cnt:i_rx_data_cnt|int_dout[2] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.234 ns" { nRxC nRxC~out0 rx:i_rx|rx_data_cnt:i_rx_data_cnt|int_dout[2] } { 0.000ns 0.000ns 1.806ns } { 0.000ns 0.868ns 0.560ns } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.232 ns" { nRxC rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.232 ns" { nRxC nRxC~out0 rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] } { 0.000ns 0.000ns 1.804ns } { 0.000ns 0.868ns 0.560ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "Rx_shift_reg.vhd" "" { Text "G:/design/summer work/download/8251/Rx_shift_reg.vhd" 85 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "Rx_data_cnt.vhd" "" { Text "G:/design/summer work/download/8251/Rx_data_cnt.vhd" 108 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "6.548 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4167 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4168 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4170 rx:i_rx|rx_sync_comp:i_rx_sync_comp|cmp_dat[5]~1720 rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~246 rx:i_rx|rx_data_cnt:i_rx_data_cnt|comb_proc~284 rx:i_rx|rx_data_cnt:i_rx_data_cnt|comb_proc~287 rx:i_rx|rx_data_cnt:i_rx_data_cnt|int_dout[2] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "6.548 ns" { rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4167 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4168 rx:i_rx|rx_shift_reg:i_rx_shift_reg|par_out[5]~4170 rx:i_rx|rx_sync_comp:i_rx_sync_comp|cmp_dat[5]~1720 rx:i_rx|rx_sync_comp:i_rx_sync_comp|Equal4~246 rx:i_rx|rx_data_cnt:i_rx_data_cnt|comb_proc~284 rx:i_rx|rx_data_cnt:i_rx_data_cnt|comb_proc~287 rx:i_rx|rx_data_cnt:i_rx_data_cnt|int_dout[2] } { 0.000ns 0.980ns 0.139ns 0.360ns 1.117ns 0.336ns 0.867ns 0.369ns 0.366ns } { 0.000ns 0.213ns 0.087ns 0.213ns 0.087ns 0.332ns 0.087ns 0.213ns 0.782ns } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.234 ns" { nRxC rx:i_rx|rx_data_cnt:i_rx_data_cnt|int_dout[2] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.234 ns" { nRxC nRxC~out0 rx:i_rx|rx_data_cnt:i_rx_data_cnt|int_dout[2] } { 0.000ns 0.000ns 1.806ns } { 0.000ns 0.868ns 0.560ns } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.232 ns" { nRxC rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.232 ns" { nRxC nRxC~out0 rx:i_rx|rx_shift_reg:i_rx_shift_reg|data[5] } { 0.000ns 0.000ns 1.804ns } { 0.000ns 0.868ns 0.560ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "nWR register register Wr_Ext:i_Wr_Ext\|ext_nWR~reg0 Wr_Ext:i_Wr_Ext\|ext_nWR~reg0 422.12 MHz Internal " "Info: Clock \"nWR\" Internal fmax is restricted to 422.12 MHz between source register \"Wr_Ext:i_Wr_Ext\|ext_nWR~reg0\" and destination register \"Wr_Ext:i_Wr_Ext\|ext_nWR~reg0\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.369 ns " "Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.653 ns + Longest register register " "Info: + Longest register to register delay is 0.653 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Wr_Ext:i_Wr_Ext\|ext_nWR~reg0 1 REG LC_X78_Y19_N2 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X78_Y19_N2; Fanout = 3; REG Node = 'Wr_Ext:i_Wr_Ext\|ext_nWR~reg0'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "wr_ext.vhd" "" { Text "G:/design/summer work/download/8251/wr_ext.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.418 ns) + CELL(0.235 ns) 0.653 ns Wr_Ext:i_Wr_Ext\|ext_nWR~reg0 2 REG LC_X78_Y19_N2 3 " "Info: 2: + IC(0.418 ns) + CELL(0.235 ns) = 0.653 ns; Loc. = LC_X78_Y19_N2; Fanout = 3; REG Node = 'Wr_Ext:i_Wr_Ext\|ext_nWR~reg0'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Wr_Ext:i_Wr_Ext|ext_nWR~reg0 Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "wr_ext.vhd" "" { Text "G:/design/summer work/download/8251/wr_ext.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.235 ns ( 35.99 % ) " "Info: Total cell delay = 0.235 ns ( 35.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.418 ns ( 64.01 % ) " "Info: Total interconnect delay = 0.418 ns ( 64.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Wr_Ext:i_Wr_Ext|ext_nWR~reg0 Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "0.653 ns" { Wr_Ext:i_Wr_Ext|ext_nWR~reg0 Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } { 0.000ns 0.418ns } { 0.000ns 0.235ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "nWR destination 2.578 ns + Shortest register " "Info: + Shortest clock path from clock \"nWR\" to destination register is 2.578 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.295 ns) 1.295 ns nWR 1 CLK PIN_T7 3 " "Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_T7; Fanout = 3; CLK Node = 'nWR'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { nWR } "NODE_NAME" } } { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.560 ns) 2.578 ns Wr_Ext:i_Wr_Ext\|ext_nWR~reg0 2 REG LC_X78_Y19_N2 3 " "Info: 2: + IC(0.723 ns) + CELL(0.560 ns) = 2.578 ns; Loc. = LC_X78_Y19_N2; Fanout = 3; REG Node = 'Wr_Ext:i_Wr_Ext\|ext_nWR~reg0'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.283 ns" { nWR Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "wr_ext.vhd" "" { Text "G:/design/summer work/download/8251/wr_ext.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.855 ns ( 71.96 % ) " "Info: Total cell delay = 1.855 ns ( 71.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns ( 28.04 % ) " "Info: Total interconnect delay = 0.723 ns ( 28.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.578 ns" { nWR Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "2.578 ns" { nWR nWR~out0 Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.295ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "nWR source 2.578 ns - Longest register " "Info: - Longest clock path from clock \"nWR\" to source register is 2.578 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.295 ns) 1.295 ns nWR 1 CLK PIN_T7 3 " "Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_T7; Fanout = 3; CLK Node = 'nWR'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { nWR } "NODE_NAME" } } { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.723 ns) + CELL(0.560 ns) 2.578 ns Wr_Ext:i_Wr_Ext\|ext_nWR~reg0 2 REG LC_X78_Y19_N2 3 " "Info: 2: + IC(0.723 ns) + CELL(0.560 ns) = 2.578 ns; Loc. = LC_X78_Y19_N2; Fanout = 3; REG Node = 'Wr_Ext:i_Wr_Ext\|ext_nWR~reg0'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.283 ns" { nWR Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "wr_ext.vhd" "" { Text "G:/design/summer work/download/8251/wr_ext.vhd" 67 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.855 ns ( 71.96 % ) " "Info: Total cell delay = 1.855 ns ( 71.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.723 ns ( 28.04 % ) " "Info: Total interconnect delay = 0.723 ns ( 28.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.578 ns" { nWR Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "2.578 ns" { nWR nWR~out0 Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.295ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.578 ns" { nWR Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "2.578 ns" { nWR nWR~out0 Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.295ns 0.560ns } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.578 ns" { nWR Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "2.578 ns" { nWR nWR~out0 Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.295ns 0.560ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "wr_ext.vhd" "" { Text "G:/design/summer work/download/8251/wr_ext.vhd" 67 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "wr_ext.vhd" "" { Text "G:/design/summer work/download/8251/wr_ext.vhd" 67 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.653 ns" { Wr_Ext:i_Wr_Ext|ext_nWR~reg0 Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "0.653 ns" { Wr_Ext:i_Wr_Ext|ext_nWR~reg0 Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } { 0.000ns 0.418ns } { 0.000ns 0.235ns } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.578 ns" { nWR Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "2.578 ns" { nWR nWR~out0 Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.295ns 0.560ns } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.578 ns" { nWR Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "2.578 ns" { nWR nWR~out0 Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } { 0.000ns 0.000ns 0.723ns } { 0.000ns 1.295ns 0.560ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { Wr_Ext:i_Wr_Ext|ext_nWR~reg0 } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui