a8251.tan.qmsg

8251芯片功能的vhdl描述

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "nTxC register proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|int_tx_resetn register tx:i_tx\|tx_par_gen:i_tx_par_gen\|int_parity 120.08 MHz 8.328 ns Internal " "Info: Clock \"nTxC\" has Internal fmax of 120.08 MHz between source register \"proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|int_tx_resetn\" and destination register \"tx:i_tx\|tx_par_gen:i_tx_par_gen\|int_parity\" (period= 8.328 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.978 ns + Longest register register " "Info: + Longest register to register delay is 3.978 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|int_tx_resetn 1 REG LC_X42_Y36_N6 38 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X42_Y36_N6; Fanout = 38; REG Node = 'proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|int_tx_resetn'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn } "NODE_NAME" } } { "Proc_cmd_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_cmd_reg.vhd" 192 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.446 ns) + CELL(0.087 ns) 0.533 ns tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|sr_load_sel\[0\]~77 2 COMB LC_X42_Y36_N1 6 " "Info: 2: + IC(0.446 ns) + CELL(0.087 ns) = 0.533 ns; Loc. = LC_X42_Y36_N1; Fanout = 6; COMB Node = 'tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|sr_load_sel\[0\]~77'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.533 ns" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|sr_load_sel[0]~77 } "NODE_NAME" } } { "Tx_state_mach.vhd" "" { Text "G:/design/summer work/download/8251/Tx_state_mach.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.889 ns) + CELL(0.213 ns) 1.635 ns tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|sr_load_sel\[0\]~78 3 COMB LC_X44_Y36_N1 3 " "Info: 3: + IC(0.889 ns) + CELL(0.213 ns) = 1.635 ns; Loc. = LC_X44_Y36_N1; Fanout = 3; COMB Node = 'tx:i_tx\|tx_cntrl:i_tx_cntrl\|tx_state_mach:i_tx_state_mach\|sr_load_sel\[0\]~78'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.102 ns" { tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|sr_load_sel[0]~77 tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|sr_load_sel[0]~78 } "NODE_NAME" } } { "Tx_state_mach.vhd" "" { Text "G:/design/summer work/download/8251/Tx_state_mach.vhd" 65 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.213 ns) 2.213 ns tx:i_tx\|tx_data_mux:i_tx_data_mux\|Mux2~321 4 COMB LC_X44_Y36_N7 2 " "Info: 4: + IC(0.365 ns) + CELL(0.213 ns) = 2.213 ns; Loc. = LC_X44_Y36_N7; Fanout = 2; COMB Node = 'tx:i_tx\|tx_data_mux:i_tx_data_mux\|Mux2~321'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.578 ns" { tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|sr_load_sel[0]~78 tx:i_tx|tx_data_mux:i_tx_data_mux|Mux2~321 } "NODE_NAME" } } { "Tx_data_mux.vhd" "" { Text "G:/design/summer work/download/8251/Tx_data_mux.vhd" 68 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.576 ns) + CELL(0.459 ns) 3.248 ns tx:i_tx\|tx_par_gen:i_tx_par_gen\|local_par~80 5 COMB LC_X45_Y36_N1 1 " "Info: 5: + IC(0.576 ns) + CELL(0.459 ns) = 3.248 ns; Loc. = LC_X45_Y36_N1; Fanout = 1; COMB Node = 'tx:i_tx\|tx_par_gen:i_tx_par_gen\|local_par~80'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.035 ns" { tx:i_tx|tx_data_mux:i_tx_data_mux|Mux2~321 tx:i_tx|tx_par_gen:i_tx_par_gen|local_par~80 } "NODE_NAME" } } { "Tx_par_gen.vhd" "" { Text "G:/design/summer work/download/8251/Tx_par_gen.vhd" 56 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.366 ns) + CELL(0.364 ns) 3.978 ns tx:i_tx\|tx_par_gen:i_tx_par_gen\|int_parity 6 REG LC_X45_Y36_N6 2 " "Info: 6: + IC(0.366 ns) + CELL(0.364 ns) = 3.978 ns; Loc. = LC_X45_Y36_N6; Fanout = 2; REG Node = 'tx:i_tx\|tx_par_gen:i_tx_par_gen\|int_parity'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.730 ns" { tx:i_tx|tx_par_gen:i_tx_par_gen|local_par~80 tx:i_tx|tx_par_gen:i_tx_par_gen|int_parity } "NODE_NAME" } } { "Tx_par_gen.vhd" "" { Text "G:/design/summer work/download/8251/Tx_par_gen.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.336 ns ( 33.58 % ) " "Info: Total cell delay = 1.336 ns ( 33.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.642 ns ( 66.42 % ) " "Info: Total interconnect delay = 2.642 ns ( 66.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.978 ns" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|sr_load_sel[0]~77 tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|sr_load_sel[0]~78 tx:i_tx|tx_data_mux:i_tx_data_mux|Mux2~321 tx:i_tx|tx_par_gen:i_tx_par_gen|local_par~80 tx:i_tx|tx_par_gen:i_tx_par_gen|int_parity } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.978 ns" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|sr_load_sel[0]~77 tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|sr_load_sel[0]~78 tx:i_tx|tx_data_mux:i_tx_data_mux|Mux2~321 tx:i_tx|tx_par_gen:i_tx_par_gen|local_par~80 tx:i_tx|tx_par_gen:i_tx_par_gen|int_parity } { 0.000ns 0.446ns 0.889ns 0.365ns 0.576ns 0.366ns } { 0.000ns 0.087ns 0.213ns 0.213ns 0.459ns 0.364ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "nTxC destination 3.224 ns + Shortest register " "Info: + Shortest clock path from clock \"nTxC\" to destination register is 3.224 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns nTxC 1 CLK PIN_P25 30 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_P25; Fanout = 30; CLK Node = 'nTxC'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { nTxC } "NODE_NAME" } } { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.796 ns) + CELL(0.560 ns) 3.224 ns tx:i_tx\|tx_par_gen:i_tx_par_gen\|int_parity 2 REG LC_X45_Y36_N6 2 " "Info: 2: + IC(1.796 ns) + CELL(0.560 ns) = 3.224 ns; Loc. = LC_X45_Y36_N6; Fanout = 2; REG Node = 'tx:i_tx\|tx_par_gen:i_tx_par_gen\|int_parity'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.356 ns" { nTxC tx:i_tx|tx_par_gen:i_tx_par_gen|int_parity } "NODE_NAME" } } { "Tx_par_gen.vhd" "" { Text "G:/design/summer work/download/8251/Tx_par_gen.vhd" 121 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.29 % ) " "Info: Total cell delay = 1.428 ns ( 44.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.796 ns ( 55.71 % ) " "Info: Total interconnect delay = 1.796 ns ( 55.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.224 ns" { nTxC tx:i_tx|tx_par_gen:i_tx_par_gen|int_parity } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.224 ns" { nTxC nTxC~out0 tx:i_tx|tx_par_gen:i_tx_par_gen|int_parity } { 0.000ns 0.000ns 1.796ns } { 0.000ns 0.868ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "nTxC source 3.224 ns - Longest register " "Info: - Longest clock path from clock \"nTxC\" to source register is 3.224 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns nTxC 1 CLK PIN_P25 30 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_P25; Fanout = 30; CLK Node = 'nTxC'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { nTxC } "NODE_NAME" } } { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.796 ns) + CELL(0.560 ns) 3.224 ns proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|int_tx_resetn 2 REG LC_X42_Y36_N6 38 " "Info: 2: + IC(1.796 ns) + CELL(0.560 ns) = 3.224 ns; Loc. = LC_X42_Y36_N6; Fanout = 38; REG Node = 'proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|int_tx_resetn'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.356 ns" { nTxC proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn } "NODE_NAME" } } { "Proc_cmd_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_cmd_reg.vhd" 192 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.29 % ) " "Info: Total cell delay = 1.428 ns ( 44.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.796 ns ( 55.71 % ) " "Info: Total interconnect delay = 1.796 ns ( 55.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.224 ns" { nTxC proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.224 ns" { nTxC nTxC~out0 proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn } { 0.000ns 0.000ns 1.796ns } { 0.000ns 0.868ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.224 ns" { nTxC tx:i_tx|tx_par_gen:i_tx_par_gen|int_parity } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.224 ns" { nTxC nTxC~out0 tx:i_tx|tx_par_gen:i_tx_par_gen|int_parity } { 0.000ns 0.000ns 1.796ns } { 0.000ns 0.868ns 0.560ns } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.224 ns" { nTxC proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.224 ns" { nTxC nTxC~out0 proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn } { 0.000ns 0.000ns 1.796ns } { 0.000ns 0.868ns 0.560ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "Proc_cmd_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_cmd_reg.vhd" 192 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "Tx_par_gen.vhd" "" { Text "G:/design/summer work/download/8251/Tx_par_gen.vhd" 121 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "Proc_cmd_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_cmd_reg.vhd" 192 -1 0 } } { "Tx_par_gen.vhd" "" { Text "G:/design/summer work/download/8251/Tx_par_gen.vhd" 121 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.978 ns" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|sr_load_sel[0]~77 tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|sr_load_sel[0]~78 tx:i_tx|tx_data_mux:i_tx_data_mux|Mux2~321 tx:i_tx|tx_par_gen:i_tx_par_gen|local_par~80 tx:i_tx|tx_par_gen:i_tx_par_gen|int_parity } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.978 ns" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|sr_load_sel[0]~77 tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach|sr_load_sel[0]~78 tx:i_tx|tx_data_mux:i_tx_data_mux|Mux2~321 tx:i_tx|tx_par_gen:i_tx_par_gen|local_par~80 tx:i_tx|tx_par_gen:i_tx_par_gen|int_parity } { 0.000ns 0.446ns 0.889ns 0.365ns 0.576ns 0.366ns } { 0.000ns 0.087ns 0.213ns 0.213ns 0.459ns 0.364ns } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.224 ns" { nTxC tx:i_tx|tx_par_gen:i_tx_par_gen|int_parity } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.224 ns" { nTxC nTxC~out0 tx:i_tx|tx_par_gen:i_tx_par_gen|int_parity } { 0.000ns 0.000ns 1.796ns } { 0.000ns 0.868ns 0.560ns } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.224 ns" { nTxC proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.224 ns" { nTxC nTxC~out0 proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|int_tx_resetn } { 0.000ns 0.000ns 1.796ns } { 0.000ns 0.868ns 0.560ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|cmd_reg\[6\] register proc:i_procintf\|proc_sync_reg:I_proc_sync_reg2\|int_dout\[7\] 279.72 MHz 3.575 ns Internal " "Info: Clock \"clk\" has Internal fmax of 279.72 MHz between source register \"proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|cmd_reg\[6\]\" and destination register \"proc:i_procintf\|proc_sync_reg:I_proc_sync_reg2\|int_dout\[7\]\" (period= 3.575 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.350 ns + Longest register register " "Info: + Longest register to register delay is 3.350 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|cmd_reg\[6\] 1 REG LC_X44_Y39_N2 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X44_Y39_N2; Fanout = 29; REG Node = 'proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|cmd_reg\[6\]'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] } "NODE_NAME" } } { "Proc_cmd_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_cmd_reg.vhd" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.435 ns) + CELL(0.087 ns) 0.522 ns proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|proc_resetn 2 COMB LC_X44_Y39_N4 8 " "Info: 2: + IC(0.435 ns) + CELL(0.087 ns) = 0.522 ns; Loc. = LC_X44_Y39_N4; Fanout = 8; COMB Node = 'proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|proc_resetn'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "0.522 ns" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|proc_resetn } "NODE_NAME" } } { "Proc_cmd_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_cmd_reg.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.448 ns) + CELL(0.087 ns) 2.057 ns proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|cmd_reg\[0\]~1707 3 COMB LC_X43_Y36_N9 8 " "Info: 3: + IC(1.448 ns) + CELL(0.087 ns) = 2.057 ns; Loc. = LC_X43_Y36_N9; Fanout = 8; COMB Node = 'proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|cmd_reg\[0\]~1707'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.535 ns" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|proc_resetn proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[0]~1707 } "NODE_NAME" } } { "Proc_cmd_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_cmd_reg.vhd" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.567 ns) + CELL(0.726 ns) 3.350 ns proc:i_procintf\|proc_sync_reg:I_proc_sync_reg2\|int_dout\[7\] 4 REG LC_X44_Y36_N0 2 " "Info: 4: + IC(0.567 ns) + CELL(0.726 ns) = 3.350 ns; Loc. = LC_X44_Y36_N0; Fanout = 2; REG Node = 'proc:i_procintf\|proc_sync_reg:I_proc_sync_reg2\|int_dout\[7\]'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "1.293 ns" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[0]~1707 proc:i_procintf|proc_sync_reg:I_proc_sync_reg2|int_dout[7] } "NODE_NAME" } } { "Proc_sync_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_sync_reg.vhd" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.900 ns ( 26.87 % ) " "Info: Total cell delay = 0.900 ns ( 26.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.450 ns ( 73.13 % ) " "Info: Total interconnect delay = 2.450 ns ( 73.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.350 ns" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|proc_resetn proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[0]~1707 proc:i_procintf|proc_sync_reg:I_proc_sync_reg2|int_dout[7] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.350 ns" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|proc_resetn proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[0]~1707 proc:i_procintf|proc_sync_reg:I_proc_sync_reg2|int_dout[7] } { 0.000ns 0.435ns 1.448ns 0.567ns } { 0.000ns 0.087ns 0.087ns 0.726ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.039 ns - Smallest " "Info: - Smallest clock skew is -0.039 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.125 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.125 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_R27 45 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_R27; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.805 ns) + CELL(0.560 ns) 3.125 ns proc:i_procintf\|proc_sync_reg:I_proc_sync_reg2\|int_dout\[7\] 2 REG LC_X44_Y36_N0 2 " "Info: 2: + IC(1.805 ns) + CELL(0.560 ns) = 3.125 ns; Loc. = LC_X44_Y36_N0; Fanout = 2; REG Node = 'proc:i_procintf\|proc_sync_reg:I_proc_sync_reg2\|int_dout\[7\]'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.365 ns" { clk proc:i_procintf|proc_sync_reg:I_proc_sync_reg2|int_dout[7] } "NODE_NAME" } } { "Proc_sync_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_sync_reg.vhd" 96 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 42.24 % ) " "Info: Total cell delay = 1.320 ns ( 42.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.805 ns ( 57.76 % ) " "Info: Total interconnect delay = 1.805 ns ( 57.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.125 ns" { clk proc:i_procintf|proc_sync_reg:I_proc_sync_reg2|int_dout[7] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.125 ns" { clk clk~out0 proc:i_procintf|proc_sync_reg:I_proc_sync_reg2|int_dout[7] } { 0.000ns 0.000ns 1.805ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.164 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.164 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns clk 1 CLK PIN_R27 45 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_R27; Fanout = 45; CLK Node = 'clk'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.844 ns) + CELL(0.560 ns) 3.164 ns proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|cmd_reg\[6\] 2 REG LC_X44_Y39_N2 29 " "Info: 2: + IC(1.844 ns) + CELL(0.560 ns) = 3.164 ns; Loc. = LC_X44_Y39_N2; Fanout = 29; REG Node = 'proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|cmd_reg\[6\]'" {  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "2.404 ns" { clk proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] } "NODE_NAME" } } { "Proc_cmd_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_cmd_reg.vhd" 140 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.320 ns ( 41.72 % ) " "Info: Total cell delay = 1.320 ns ( 41.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.844 ns ( 58.28 % ) " "Info: Total interconnect delay = 1.844 ns ( 58.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.164 ns" { clk proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.164 ns" { clk clk~out0 proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] } { 0.000ns 0.000ns 1.844ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.125 ns" { clk proc:i_procintf|proc_sync_reg:I_proc_sync_reg2|int_dout[7] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.125 ns" { clk clk~out0 proc:i_procintf|proc_sync_reg:I_proc_sync_reg2|int_dout[7] } { 0.000ns 0.000ns 1.805ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.164 ns" { clk proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.164 ns" { clk clk~out0 proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] } { 0.000ns 0.000ns 1.844ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" {  } { { "Proc_cmd_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_cmd_reg.vhd" 140 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "Proc_sync_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_sync_reg.vhd" 96 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.350 ns" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|proc_resetn proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[0]~1707 proc:i_procintf|proc_sync_reg:I_proc_sync_reg2|int_dout[7] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.350 ns" { proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|proc_resetn proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[0]~1707 proc:i_procintf|proc_sync_reg:I_proc_sync_reg2|int_dout[7] } { 0.000ns 0.435ns 1.448ns 0.567ns } { 0.000ns 0.087ns 0.087ns 0.726ns } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.125 ns" { clk proc:i_procintf|proc_sync_reg:I_proc_sync_reg2|int_dout[7] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.125 ns" { clk clk~out0 proc:i_procintf|proc_sync_reg:I_proc_sync_reg2|int_dout[7] } { 0.000ns 0.000ns 1.805ns } { 0.000ns 0.760ns 0.560ns } } } { "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera1/quartus6.0/win/TimingClosureFloorplan.fld" "" "3.164 ns" { clk proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] } "NODE_NAME" } } { "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera1/quartus6.0/win/Technology_Viewer.qrui" "3.164 ns" { clk clk~out0 proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg|cmd_reg[6] } { 0.000ns 0.000ns 1.844ns } { 0.000ns 0.760ns 0.560ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}