a8251.tan.qmsg

8251芯片功能的vhdl描述

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "nTxC " "Info: Assuming node \"nTxC\" is an undefined clock" {  } { { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 45 -1 0 } } { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "nTxC" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 36 -1 0 } } { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "nRxC " "Info: Assuming node \"nRxC\" is an undefined clock" {  } { { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 46 -1 0 } } { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "nRxC" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "nWR " "Info: Assuming node \"nWR\" is an undefined clock" {  } { { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 38 -1 0 } } { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "nWR" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "nCS " "Info: Assuming node \"nCS\" is an undefined clock" {  } { { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 40 -1 0 } } { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "nCS" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "CnD " "Info: Assuming node \"CnD\" is an undefined clock" {  } { { "A8251.vhd" "" { Text "G:/design/summer work/download/8251/A8251.vhd" 41 -1 0 } } { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "CnD" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "4 " "Warning: Found 4 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "proc:i_procintf\|proc_sm:I_proc_sm\|init_done " "Info: Detected ripple clock \"proc:i_procintf\|proc_sm:I_proc_sm\|init_done\" as buffer" {  } { { "Proc_sm.vhd" "" { Text "G:/design/summer work/download/8251/Proc_sm.vhd" 49 -1 0 } } { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "proc:i_procintf\|proc_sm:I_proc_sm\|init_done" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "proc:i_procintf\|proc_dec:I_proc_dec\|decode~53 " "Info: Detected gated clock \"proc:i_procintf\|proc_dec:I_proc_dec\|decode~53\" as buffer" {  } { { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "proc:i_procintf\|proc_dec:I_proc_dec\|decode~53" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "proc:i_procintf\|proc_dec:I_proc_dec\|decode~52 " "Info: Detected gated clock \"proc:i_procintf\|proc_dec:I_proc_dec\|decode~52\" as buffer" {  } { { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "proc:i_procintf\|proc_dec:I_proc_dec\|decode~52" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|cmd_reg\[4\] " "Info: Detected ripple clock \"proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|cmd_reg\[4\]\" as buffer" {  } { { "Proc_cmd_reg.vhd" "" { Text "G:/design/summer work/download/8251/Proc_cmd_reg.vhd" 140 -1 0 } } { "d:/altera1/quartus6.0/win/Assignment Editor.qase" "" { Assignment "d:/altera1/quartus6.0/win/Assignment Editor.qase" 1 { { 0 "proc:i_procintf\|proc_cmd_reg:I_proc_cmd_reg\|cmd_reg\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}