a8251.hier_info

8251芯片功能的vhdl描述

txdin[1] => tx_data_mux:i_tx_data_mux.di[1]
txdin[2] => tx_data_mux:i_tx_data_mux.di[2]
txdin[3] => tx_data_mux:i_tx_data_mux.di[3]
txdin[4] => tx_data_mux:i_tx_data_mux.di[4]
txdin[5] => tx_data_mux:i_tx_data_mux.di[5]
txdin[6] => tx_data_mux:i_tx_data_mux.di[6]
txdin[7] => tx_data_mux:i_tx_data_mux.di[7]
sync_char1[0] => tx_data_mux:i_tx_data_mux.sync_char1[0]
sync_char1[1] => tx_data_mux:i_tx_data_mux.sync_char1[1]
sync_char1[2] => tx_data_mux:i_tx_data_mux.sync_char1[2]
sync_char1[3] => tx_data_mux:i_tx_data_mux.sync_char1[3]
sync_char1[4] => tx_data_mux:i_tx_data_mux.sync_char1[4]
sync_char1[5] => tx_data_mux:i_tx_data_mux.sync_char1[5]
sync_char1[6] => tx_data_mux:i_tx_data_mux.sync_char1[6]
sync_char1[7] => tx_data_mux:i_tx_data_mux.sync_char1[7]
sync_char2[0] => tx_data_mux:i_tx_data_mux.sync_char2[0]
sync_char2[1] => tx_data_mux:i_tx_data_mux.sync_char2[1]
sync_char2[2] => tx_data_mux:i_tx_data_mux.sync_char2[2]
sync_char2[3] => tx_data_mux:i_tx_data_mux.sync_char2[3]
sync_char2[4] => tx_data_mux:i_tx_data_mux.sync_char2[4]
sync_char2[5] => tx_data_mux:i_tx_data_mux.sync_char2[5]
sync_char2[6] => tx_data_mux:i_tx_data_mux.sync_char2[6]
sync_char2[7] => tx_data_mux:i_tx_data_mux.sync_char2[7]
tx_fifo_rd_n <= tx_cntrl:i_tx_cntrl.tx_fifo_rd_n
tx_sr_empty_n <= tx_cntrl:i_tx_cntrl.tx_sr_empty_n
txdata <= tx_line_mux:i_tx_line_mux.txdata


|A8251|tx:i_tx|tx_cntrl:i_tx_cntrl
reset => tx_clk_div:i_tx_clk_div.reset
reset => tx_data_cnt:i_tx_data_cnt.reset
reset => tx_state_mach:i_tx_state_mach.sys_reset
txclk => tx_clk_div:i_tx_clk_div.txclk
txclk => tx_data_cnt:i_tx_data_cnt.clk
txclk => tx_state_mach:i_tx_state_mach.tx_clk
tx_resetn => tx_state_mach:i_tx_state_mach.tx_reset
parity_en => tx_state_mach:i_tx_state_mach.parity_en
s1 => tx_state_mach:i_tx_state_mach.s1
s2 => tx_state_mach:i_tx_state_mach.s2
b1 => tx_clk_div:i_tx_clk_div.b1
b1 => tx_state_mach:i_tx_state_mach.b1
b2 => tx_clk_div:i_tx_clk_div.b2
b2 => tx_state_mach:i_tx_state_mach.b2
l1 => tx_data_cnt:i_tx_data_cnt.l1
l2 => tx_data_cnt:i_tx_data_cnt.l2
tx_en => tx_state_mach:i_tx_state_mach.tx_en
tx_fifo_ef_n => tx_state_mach:i_tx_state_mach.tx_fifo_ef_n
cts => tx_state_mach:i_tx_state_mach.cts
tx_sr_empty_n <= tx_state_mach:i_tx_state_mach.tx_sr_empty_n
mux_cntl[0] <= tx_state_mach:i_tx_state_mach.mux_cntl[0]
mux_cntl[1] <= tx_state_mach:i_tx_state_mach.mux_cntl[1]
shift_en <= tx_state_mach:i_tx_state_mach.shift_en
tx_fifo_rd_n <= tx_state_mach:i_tx_state_mach.tx_fifo_rd_n
sr_load_en <= tx_state_mach:i_tx_state_mach.sr_load_en
sr_load_sel[0] <= tx_state_mach:i_tx_state_mach.sr_load_sel[0]
sr_load_sel[1] <= tx_state_mach:i_tx_state_mach.sr_load_sel[1]


|A8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_state_mach:i_tx_state_mach
sys_reset => tx_fifo_rd_n~reg0.PRESET
sys_reset => state~1.IN1
tx_clk => tx_fifo_rd_n~reg0.CLK
tx_clk => state~0.IN1
tx_reset => next_state.init.OUTPUTSELECT
tx_reset => next_state.start.OUTPUTSELECT
tx_reset => next_state.sync1.OUTPUTSELECT
tx_reset => next_state.sync2.OUTPUTSELECT
tx_reset => next_state.data.OUTPUTSELECT
tx_reset => next_state.parity.OUTPUTSELECT
tx_reset => next_state.stop1.OUTPUTSELECT
tx_reset => next_state.stop2.OUTPUTSELECT
tx_reset => tx_sr_empty_n~9.OUTPUTSELECT
tx_reset => next_tx_fifo_rd_n.OUTPUTSELECT
tx_reset => data_cnt_en~2.OUTPUTSELECT
tx_reset => data_cnt_clr~3.OUTPUTSELECT
tx_reset => sr_load_en~5.OUTPUTSELECT
tx_reset => sr_load_sel~5.OUTPUTSELECT
tx_reset => sr_load_sel~6.OUTPUTSELECT
tx_reset => div_cnt_en~2.OUTPUTSELECT
tx_reset => div_cnt_clr~1.OUTPUTSELECT
tx_reset => shift_en~0.OUTPUTSELECT
tx_reset => mux_cntl~4.OUTPUTSELECT
tx_reset => mux_cntl~5.OUTPUTSELECT
data_tc => Selector5.IN3
data_tc => next_state~4.OUTPUTSELECT
data_tc => next_state~5.OUTPUTSELECT
data_tc => next_state~6.OUTPUTSELECT
data_tc => tx_sr_empty_n~2.OUTPUTSELECT
data_tc => next_tx_fifo_rd_n~2.OUTPUTSELECT
data_tc => sr_load_en~0.OUTPUTSELECT
data_tc => Selector5.IN4
data_tc => next_state~14.OUTPUTSELECT
data_tc => next_state~15.OUTPUTSELECT
data_tc => next_state~16.OUTPUTSELECT
data_tc => tx_sr_empty_n~4.OUTPUTSELECT
data_tc => next_tx_fifo_rd_n~6.OUTPUTSELECT
data_tc => Selector5.IN5
data_tc => next_state~17.OUTPUTSELECT
data_tc => data_cnt_clr~1.DATAB
data_tc => next_state~18.OUTPUTSELECT
data_tc => Selector2.IN2
data_tc => next_state~19.DATAB
b1 => statetran~0.IN0
b2 => statetran~0.IN1
tc => Selector18.IN4
tc => Selector14.IN3
tc => Selector18.IN5
tc => data_cnt_en~0.DATAB
tc => data_cnt_clr~1.OUTPUTSELECT
tc => next_state~19.OUTPUTSELECT
tc => next_state~20.OUTPUTSELECT
tc => next_state~21.OUTPUTSELECT
tc => Selector16.IN4
tc => Selector18.IN6
tc => Selector18.IN7
tc => next_state~22.OUTPUTSELECT
tc => sr_load_en~2.OUTPUTSELECT
tc => next_tx_fifo_rd_n~8.OUTPUTSELECT
tc => tx_sr_empty_n~6.OUTPUTSELECT
tc => statetran~4.IN0
tc => Selector15.IN2
tc => Selector16.IN2
tc => Selector13.IN1
half_tc => statetran~5.IN1
tx_en => statetran~1.IN1
tx_en => statetran~3.IN1
tx_fifo_ef_n => next_state~1.DATAB
tx_fifo_ef_n => statetran~2.IN1
tx_fifo_ef_n => tx_sr_empty_n~0.DATAB
tx_fifo_ef_n => next_state~7.OUTPUTSELECT
tx_fifo_ef_n => next_tx_fifo_rd_n~3.OUTPUTSELECT
tx_fifo_ef_n => sr_load_sel~0.OUTPUTSELECT
tx_fifo_ef_n => next_state~0.DATAB
tx_fifo_ef_n => next_tx_fifo_rd_n~0.DATAB
tx_fifo_ef_n => Selector9.IN1
tx_fifo_ef_n => Selector9.IN2
tx_fifo_ef_n => Selector9.IN3
cts => statetran~2.IN0
cts => statetran~1.IN0
parity_en => next_state~2.OUTPUTSELECT
parity_en => next_state~3.OUTPUTSELECT
parity_en => tx_sr_empty_n~1.OUTPUTSELECT
parity_en => next_tx_fifo_rd_n~1.OUTPUTSELECT
parity_en => next_state~11.OUTPUTSELECT
parity_en => next_state~12.OUTPUTSELECT
parity_en => next_state~13.OUTPUTSELECT
parity_en => tx_sr_empty_n~3.OUTPUTSELECT
parity_en => next_tx_fifo_rd_n~5.OUTPUTSELECT
parity_en => next_state~18.DATAB
parity_en => sr_load_en~0.DATAB
s1 => statetran~4.IN1
s1 => statetran~5.IN0
s2 => sr_load_sel~0.DATAB
s2 => next_state~7.DATAA
s2 => next_state~22.DATAB
s2 => sr_load_en~1.OUTPUTSELECT
s2 => next_tx_fifo_rd_n~7.OUTPUTSELECT
s2 => tx_sr_empty_n~5.OUTPUTSELECT
s2 => sr_load_sel~1.DATAB
s2 => next_state~9.DATAB
s2 => next_tx_fifo_rd_n~3.DATAA
data_cnt_en <= data_cnt_en~2.DB_MAX_OUTPUT_PORT_TYPE
data_cnt_clr <= data_cnt_clr~3.DB_MAX_OUTPUT_PORT_TYPE
tx_sr_empty_n <= tx_sr_empty_n~9.DB_MAX_OUTPUT_PORT_TYPE
tx_fifo_rd_n <= tx_fifo_rd_n~reg0.DB_MAX_OUTPUT_PORT_TYPE
div_cnt_en <= div_cnt_en~2.DB_MAX_OUTPUT_PORT_TYPE
div_cnt_clr <= div_cnt_clr~1.DB_MAX_OUTPUT_PORT_TYPE
shift_en <= shift_en~0.DB_MAX_OUTPUT_PORT_TYPE
sr_load_en <= sr_load_en~5.DB_MAX_OUTPUT_PORT_TYPE
sr_load_sel[0] <= sr_load_sel~6.DB_MAX_OUTPUT_PORT_TYPE
sr_load_sel[1] <= sr_load_sel~5.DB_MAX_OUTPUT_PORT_TYPE
mux_cntl[0] <= mux_cntl~5.DB_MAX_OUTPUT_PORT_TYPE
mux_cntl[1] <= mux_cntl~4.DB_MAX_OUTPUT_PORT_TYPE


|A8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_data_cnt:i_tx_data_cnt
reset => data_tc~0.OUTPUTSELECT
reset => comb_proc~0.IN0
reset => bit_cnt[0].ACLR
reset => bit_cnt[1].ACLR
reset => bit_cnt[2].ACLR
clk => bit_cnt[0].CLK
clk => bit_cnt[1].CLK
clk => bit_cnt[2].CLK
sclr => comb_proc~0.IN1
ce => next_bit_cnt~0.OUTPUTSELECT
ce => next_bit_cnt~1.OUTPUTSELECT
ce => next_bit_cnt~2.OUTPUTSELECT
l1 => Equal0.IN2
l2 => Equal0.IN1
data_tc <= data_tc~0.DB_MAX_OUTPUT_PORT_TYPE


|A8251|tx:i_tx|tx_cntrl:i_tx_cntrl|tx_clk_div:i_tx_clk_div
txclk => int_dout[0].CLK
txclk => int_dout[1].CLK
txclk => int_dout[2].CLK
txclk => int_dout[3].CLK
txclk => int_dout[4].CLK
txclk => int_dout[5].CLK
txclk => int_dout[6].CLK
reset => int_dout[0].ACLR
reset => int_dout[1].ACLR
reset => int_dout[2].ACLR
reset => int_dout[3].ACLR
reset => int_dout[4].ACLR
reset => int_dout[5].ACLR
reset => int_dout[6].ACLR
clr_cnt => mux_dout[6].OUTPUTSELECT
clr_cnt => mux_dout[5].OUTPUTSELECT
clr_cnt => mux_dout[4].OUTPUTSELECT
clr_cnt => mux_dout[3].OUTPUTSELECT
clr_cnt => mux_dout[2].OUTPUTSELECT
clr_cnt => mux_dout[1].OUTPUTSELECT
clr_cnt => mux_dout[0].OUTPUTSELECT
count_en => half_tc~0.IN0
count_en => tc~0.IN0
count_en => mux_dout~0.OUTPUTSELECT
count_en => mux_dout~1.OUTPUTSELECT
count_en => mux_dout~2.OUTPUTSELECT
count_en => mux_dout~3.OUTPUTSELECT
count_en => mux_dout~4.OUTPUTSELECT
count_en => mux_dout~5.OUTPUTSELECT
count_en => mux_dout~6.OUTPUTSELECT
b1 => comp_one[5].DATAA
b1 => comp_one[4].DATAA
b1 => comp_half[4].DATAA
b1 => comp_half[3].DATAA
b2 => comp_one[5].OUTPUTSELECT
b2 => comp_one[4].OUTPUTSELECT
b2 => comp_half[4].OUTPUTSELECT
b2 => comp_half[3].OUTPUTSELECT
b2 => comb_proc~1.IN0
b2 => comb_proc~0.IN0
b2 => Equal0.IN3
b2 => Equal0.IN4
b2 => Equal0.IN5
b2 => Equal0.IN6
b2 => Equal1.IN4
b2 => Equal1.IN5
b2 => Equal1.IN6
half_tc <= half_tc~0.DB_MAX_OUTPUT_PORT_TYPE
tc <= tc~0.DB_MAX_OUTPUT_PORT_TYPE


|A8251|tx:i_tx|tx_data_mux:i_tx_data_mux
di[0] => Mux7.IN1
di[1] => Mux6.IN1
di[2] => Mux5.IN1
di[3] => Mux4.IN1
di[4] => Mux3.IN1
di[5] => data~5.DATAA
di[6] => data~2.DATAA
di[7] => data~0.DATAA
sync_char1[0] => Mux7.IN2
sync_char1[1] => Mux6.IN2
sync_char1[2] => Mux5.IN2
sync_char1[3] => Mux4.IN2
sync_char1[4] => Mux3.IN2
sync_char1[5] => data~11.DATAA
sync_char1[6] => data~8.DATAA
sync_char1[7] => data~6.DATAA
sync_char2[0] => Mux7.IN3
sync_char2[1] => Mux6.IN3
sync_char2[2] => Mux5.IN3
sync_char2[3] => Mux4.IN3
sync_char2[4] => Mux3.IN3
sync_char2[5] => data~17.DATAA
sync_char2[6] => data~14.DATAA
sync_char2[7] => data~12.DATAA
sr_load_sel[0] => Mux0.IN5
sr_load_sel[0] => Mux1.IN5
sr_load_sel[0] => Mux2.IN5
sr_load_sel[0] => Mux3.IN5
sr_load_sel[0] => Mux4.IN5
sr_load_sel[0] => Mux5.IN5
sr_load_sel[0] => Mux6.IN5
sr_load_sel[0] => Mux7.IN5
sr_load_sel[1] => Mux0.IN4
sr_load_sel[1] => Mux1.IN4
sr_load_sel[1] => Mux2.IN4
sr_load_sel[1] => Mux3.IN4
sr_load_sel[1] => Mux4.IN4
sr_load_sel[1] => Mux5.IN4
sr_load_sel[1] => Mux6.IN4
sr_load_sel[1] => Mux7.IN4
l1 => output~1.IN1
l1 => output~2.IN1
l1 => output~0.IN1
l2 => output~2.IN0
l2 => output~1.IN0
l2 => output~0.IN0
data[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
data[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
data[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
data[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
data[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
data[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
data[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
data[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE


|A8251|tx:i_tx|tx_par_gen:i_tx_par_gen
data[0] => temp_par~0.IN1
data[1] => temp_par~0.IN0
data[2] => temp_par~1.IN1
data[3] => temp_par~2.IN1
data[4] => temp_par~3.IN1
data[5] => temp_par~4.IN1
data[6] => temp_par~5.IN1
data[7] => temp_par~6.IN1
parity_even => local_par.OUTPUTSELECT
sr_load_en => int_parity.ENA
txclk => int_parity.CLK
reset => int_parity.ACLR
parity <= int_parity.DB_MAX_OUTPUT_PORT_TYPE


|A8251|tx:i_tx|tx_shift_reg:i_tx_shift_reg
txclk => data_int[0].CLK
txclk => data_int[1].CLK
txclk => data_int[2].CLK
txclk => data_int[3].CLK
txclk => data_int[4].CLK
txclk => data_int[5].CLK
txclk => data_int[6].CLK
txclk => data_int[7].CLK
reset => data_int[0].ACLR
reset => data_int[1].ACLR
reset => data_int[2].ACLR
reset => data_int[3].ACLR
reset => data_int[4].ACLR
reset => data_int[5].ACLR
reset => data_int[6].ACLR
reset => data_int[7].ACLR
data[0] => next_data~15.DATAB
data[1] => next_data~14.DATAB
data[2] => next_data~13.DATAB
data[3] => next_data~12.DATAB
data[4] => next_data~11.DATAB
data[5] => next_data~10.DATAB
data[6] => next_data~9.DATAB
data[7] => next_data~8.DATAB
sync_rst => next_data[7].OUTPUTSELECT
sync_rst => next_data[6].OUTPUTSELECT
sync_rst => next_data[5].OUTPUTSELECT
sync_rst => next_data[4].OUTPUTSELECT
sync_rst => next_data[3].OUTPUTSELECT
sync_rst => next_data[2].OUTPUTSELECT
sync_rst => next_data[1].OUTPUTSELECT
sync_rst => next_data[0].OUTPUTSELECT
shift_en => next_data~0.OUTPUTSELECT
shift_en => next_data~1.OUTPUTSELECT
shift_en => next_data~2.OUTPUTSELECT
shift_en => next_data~3.OUTPUTSELECT
shift_en => next_data~4.OUTPUTSELECT
shift_en => next_data~5.OUTPUTSELECT
shift_en => next_data~6.OUTPUTSELECT
shift_en => next_data~7.OUTPUTSELECT
sr_load_en => next_data~8.OUTPUTSELECT
sr_load_en => next_data~9.OUTPUTSELECT
sr_load_en => next_data~10.OUTPUTSELECT
sr_load_en => next_data~11.OUTPUTSELECT
sr_load_en => next_data~12.OUTPUTSELECT
sr_load_en => next_data~13.OUTPUTSELECT
sr_load_en => next_data~14.OUTPUTSELECT
sr_load_en => next_data~15.OUTPUTSELECT
data_out <= data_int[0].DB_MAX_OUTPUT_PORT_TYPE


|A8251|tx:i_tx|tx_line_mux:i_tx_line_mux
data_out => txdata~1.DATAB
parity => txdata~0.DATAB
mux_cntl[0] => Equal0.IN1
mux_cntl[0] => Equal1.IN1
mux_cntl[0] => Equal2.IN0
mux_cntl[1] => Equal0.IN0
mux_cntl[1] => Equal1.IN0
mux_cntl[1] => Equal2.IN1
break_en => txdata~2.OUTPUTSELECT
txdata <= txdata~2.DB_MAX_OUTPUT_PORT_TYPE


|A8251|tx_fifo:i_tx_fifo
rst_n => ff_wr_proc~0.IN1
tx_rst_n => ff_wr_proc~0.IN0
wr_n => int_ff.CLK
wr_n => q[0]~reg0.CLK
wr_n => q[1]~reg0.CLK
wr_n => q[2]~reg0.CLK
wr_n => q[3]~reg0.CLK
wr_n => q[4]~reg0.CLK
wr_n => q[5]~reg0.CLK
wr_n => q[6]~reg0.CLK
wr_n => q[7]~reg0.CLK
rd_clk => ff_clr.CLK
rd_n => ff_clr.DATAIN
d[0] => q[0]~reg0.DATAIN
d[1] => q[1]~reg0.DATAIN
d[2] => q[2]~reg0.DATAIN
d[3] => q[3]~reg0.DATAIN
d[4] => q[4]~reg0.DATAIN
d[5] => q[5]~reg0.DATAIN
d[6] => q[6]~reg0.DATAIN
d[7] => q[7]~reg0.DATAIN
ef_n <= int_ff.DB_MAX_OUTPUT_PORT_TYPE
ff_n <= int_ff.DB_MAX_OUTPUT_PORT_TYPE
q[0] <= q[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[1] <= q[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[2] <= q[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[3] <= q[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[4] <= q[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[5] <= q[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[6] <= q[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
q[7] <= q[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE