a8251.hier_info

8251芯片功能的vhdl描述

hunt => Selector2.IN3
hunt => next_state~6.OUTPUTSELECT
hunt => next_state~7.OUTPUTSELECT
hunt => int_syncdet~1.OUTPUTSELECT
hunt => Selector2.IN4
hunt => next_state~8.OUTPUTSELECT
data_tc => statetran~4.IN1
data_tc => statetran~5.IN1
tran_en => statetran~6.IN1
tran_en => statetran~7.IN0
tran_en => statetran~8.IN1
b1 => statetran~0.IN1
b2 => statetran~1.IN1
int_syncdet <= int_syncdet~3.DB_MAX_OUTPUT_PORT_TYPE
sync_en <= en_sync~2.DB_MAX_OUTPUT_PORT_TYPE
en_cnt <= en_cnt~1.DB_MAX_OUTPUT_PORT_TYPE
clr_cnt <= clr_cnt~2.DB_MAX_OUTPUT_PORT_TYPE
sync_ce <= sync_ce~1.DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_sync_comp:i_rx_sync_comp
l1 => Equal0.IN1
l1 => Equal1.IN0
l1 => Equal2.IN1
l2 => Equal0.IN0
l2 => Equal1.IN1
l2 => Equal2.IN0
en_sync => cmp_dat[7].OUTPUTSELECT
en_sync => cmp_dat[6].OUTPUTSELECT
en_sync => cmp_dat[5].OUTPUTSELECT
en_sync => cmp_dat[4].OUTPUTSELECT
en_sync => cmp_dat[3].OUTPUTSELECT
en_sync => cmp_dat[2].OUTPUTSELECT
en_sync => cmp_dat[1].OUTPUTSELECT
en_sync => cmp_dat[0].OUTPUTSELECT
rx_reg[0] => cmp_dat[0].DATAA
rx_reg[1] => cmp_dat[1].DATAA
rx_reg[2] => cmp_dat[2].DATAA
rx_reg[3] => cmp_dat[3].DATAA
rx_reg[4] => cmp_dat[4].DATAA
rx_reg[5] => cmp_dat[5].DATAA
rx_reg[6] => cmp_dat[6].DATAA
rx_reg[7] => cmp_dat[7].DATAA
rx_data[0] => cmp_dat[0].DATAB
rx_data[1] => cmp_dat[1].DATAB
rx_data[2] => cmp_dat[2].DATAB
rx_data[3] => cmp_dat[3].DATAB
rx_data[4] => cmp_dat[4].DATAB
rx_data[5] => cmp_dat[5].DATAB
rx_data[6] => cmp_dat[6].DATAB
rx_data[7] => cmp_dat[7].DATAB
sync_char1[0] => Equal3.IN7
sync_char1[1] => Equal3.IN6
sync_char1[2] => Equal3.IN5
sync_char1[3] => Equal3.IN4
sync_char1[4] => Equal3.IN3
sync_char1[5] => char1~0.DATAB
sync_char1[5] => char1~2.DATAB
sync_char1[5] => char1[5].DATAB
sync_char1[6] => char1~1.DATAB
sync_char1[6] => char1[6].DATAB
sync_char1[7] => char1[7].DATAB
sync_char2[0] => Equal4.IN7
sync_char2[1] => Equal4.IN6
sync_char2[2] => Equal4.IN5
sync_char2[3] => Equal4.IN4
sync_char2[4] => Equal4.IN3
sync_char2[5] => char2~0.DATAB
sync_char2[5] => char2~2.DATAB
sync_char2[5] => char2[5].DATAB
sync_char2[6] => char2~1.DATAB
sync_char2[6] => char2[6].DATAB
sync_char2[7] => char2[7].DATAB
sync1_eq <= Equal3.DB_MAX_OUTPUT_PORT_TYPE
sync2_eq <= Equal4.DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_shift_reg:i_rx_shift_reg
clock => data[0].CLK
clock => data[1].CLK
clock => data[2].CLK
clock => data[3].CLK
clock => data[4].CLK
clock => data[5].CLK
clock => data[6].CLK
clock => data[7].CLK
clock => data[8].CLK
reset => word_length[1].OUTPUTSELECT
reset => word_length[0].OUTPUTSELECT
reset => data[0].ACLR
reset => data[1].ACLR
reset => data[2].ACLR
reset => data[3].ACLR
reset => data[4].ACLR
reset => data[5].ACLR
reset => data[6].ACLR
reset => data[7].ACLR
reset => data[8].ACLR
sclr => next_data[8].OUTPUTSELECT
sclr => next_data[7].OUTPUTSELECT
sclr => next_data[6].OUTPUTSELECT
sclr => next_data[5].OUTPUTSELECT
sclr => next_data[4].OUTPUTSELECT
sclr => next_data[3].OUTPUTSELECT
sclr => next_data[2].OUTPUTSELECT
sclr => next_data[1].OUTPUTSELECT
sclr => next_data[0].OUTPUTSELECT
shift_en => next_data~0.OUTPUTSELECT
shift_en => next_data~1.OUTPUTSELECT
shift_en => next_data~2.OUTPUTSELECT
shift_en => next_data~3.OUTPUTSELECT
shift_en => next_data~4.OUTPUTSELECT
shift_en => next_data~5.OUTPUTSELECT
shift_en => next_data~6.OUTPUTSELECT
shift_en => next_data~7.OUTPUTSELECT
shift_en => next_data~8.OUTPUTSELECT
l1 => word_length[0].DATAB
l2 => word_length[1].DATAB
parity_en => par_out~0.IN1
parity_en => par_out~13.IN0
parity_en => par_out~28.IN0
parity_en => par_out~45.IN0
parity_en => par_out~36.IN0
parity_en => par_out~20.IN0
parity_en => par_out~6.IN0
sli => next_data~0.DATAB
parity <= data[8].DB_MAX_OUTPUT_PORT_TYPE
par_out[0] <= par_out~53.DB_MAX_OUTPUT_PORT_TYPE
par_out[1] <= par_out~52.DB_MAX_OUTPUT_PORT_TYPE
par_out[2] <= par_out~51.DB_MAX_OUTPUT_PORT_TYPE
par_out[3] <= par_out~50.DB_MAX_OUTPUT_PORT_TYPE
par_out[4] <= par_out~49.DB_MAX_OUTPUT_PORT_TYPE
par_out[5] <= par_out~48.DB_MAX_OUTPUT_PORT_TYPE
par_out[6] <= par_out~47.DB_MAX_OUTPUT_PORT_TYPE
par_out[7] <= par_out~46.DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_data_reg:i_rx_data_reg
clk => int_dout[0].CLK
clk => int_dout[1].CLK
clk => int_dout[2].CLK
clk => int_dout[3].CLK
clk => int_dout[4].CLK
clk => int_dout[5].CLK
clk => int_dout[6].CLK
clk => int_dout[7].CLK
clr => int_dout[0].ACLR
clr => int_dout[1].ACLR
clr => int_dout[2].ACLR
clr => int_dout[3].ACLR
clr => int_dout[4].ACLR
clr => int_dout[5].ACLR
clr => int_dout[6].ACLR
clr => int_dout[7].ACLR
sclr => mux_dout[7].OUTPUTSELECT
sclr => mux_dout[6].OUTPUTSELECT
sclr => mux_dout[5].OUTPUTSELECT
sclr => mux_dout[4].OUTPUTSELECT
sclr => mux_dout[3].OUTPUTSELECT
sclr => mux_dout[2].OUTPUTSELECT
sclr => mux_dout[1].OUTPUTSELECT
sclr => mux_dout[0].OUTPUTSELECT
ce => mux_dout~6.OUTPUTSELECT
ce => mux_dout~7.OUTPUTSELECT
ce => mux_dout~8.OUTPUTSELECT
ce => mux_dout~9.OUTPUTSELECT
ce => mux_dout~10.OUTPUTSELECT
ce => mux_dout~11.OUTPUTSELECT
ce => mux_dout~12.OUTPUTSELECT
ce => mux_dout~13.OUTPUTSELECT
l1 => Equal0.IN1
l1 => Equal1.IN1
l1 => Equal2.IN0
l2 => Equal0.IN0
l2 => Equal1.IN0
l2 => Equal2.IN1
d[0] => mux_dout~13.DATAB
d[1] => mux_dout~12.DATAB
d[2] => mux_dout~11.DATAB
d[3] => mux_dout~10.DATAB
d[4] => mux_dout~9.DATAB
d[5] => mux_dout~5.DATAA
d[6] => mux_dout~2.DATAA
d[7] => mux_dout~0.DATAA
q[0] <= int_dout[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= int_dout[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= int_dout[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= int_dout[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= int_dout[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= int_dout[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= int_dout[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= int_dout[7].DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_data_cnt:i_rx_data_cnt
reset => comp_one[3].OUTPUTSELECT
reset => comp_one[2].OUTPUTSELECT
reset => comp_one[1].OUTPUTSELECT
reset => comp_one[0].OUTPUTSELECT
reset => int_tc~0.OUTPUTSELECT
reset => comb_proc~3.IN1
reset => int_dout[0].ACLR
reset => int_dout[1].ACLR
reset => int_dout[2].ACLR
reset => int_dout[3].ACLR
clk => int_dout[0].CLK
clk => int_dout[1].CLK
clk => int_dout[2].CLK
clk => int_dout[3].CLK
clr_cnt => comb_proc~1.IN1
dat_clr => comb_proc~0.IN1
shift_en => comb_proc~4.IN0
parity_en => comp_one~1.IN1
parity_en => comp_one~12.IN0
parity_en => comp_one~25.IN0
parity_en => comp_one~38.IN0
parity_en => comp_one~5.IN1
parity_en => comp_one~18.IN0
parity_en => comp_one~31.IN0
parity_en => comp_one~44.IN0
en_sync => comb_proc~1.IN0
en_sync => comb_proc~4.IN1
en_sync => comp_one~2.IN0
en_sync => comp_one~6.IN0
en_sync => comp_one~13.IN0
en_sync => comp_one~19.IN0
en_sync => comp_one~26.IN0
en_sync => comp_one~32.IN0
en_sync => comp_one~39.IN0
en_sync => comp_one~45.IN0
en_sync => comb_proc~0.IN0
l1 => comp_one~0.IN0
l1 => comp_one~4.DATAA
l1 => comp_one~24.IN0
l1 => comp_one~11.IN0
l1 => comp_one~37.IN0
l2 => comp_one~0.IN1
l2 => comp_one~3.DATAA
l2 => comp_one~11.IN1
l2 => comp_one~24.IN1
l2 => comp_one~37.IN1
data_tc <= int_tc~0.DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_par_tree:i_rx_par_tree
even_parity => parity.OUTPUTSELECT
parity_en => parity_err~1.OUTPUTSELECT
rx_parity => parity_err~0.IN0
din[0] => temp_par~0.IN1
din[1] => temp_par~0.IN0
din[2] => temp_par~1.IN1
din[3] => temp_par~2.IN1
din[4] => temp_par~3.IN1
din[5] => temp_par~4.IN1
din[6] => temp_par~5.IN1
din[7] => temp_par~6.IN1
parity_err <= parity_err~1.DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_error_reg:i1_rx_error_reg
clk => int_dout.CLK
reset => sync_proc~0.IN0
clr_error_n => sync_proc~0.IN1
enable_error => comb_proc~0.IN0
set_error => comb_proc~0.IN1
error <= int_dout.DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_error_reg:i2_rx_error_reg
clk => int_dout.CLK
reset => sync_proc~0.IN0
clr_error_n => sync_proc~0.IN1
enable_error => comb_proc~0.IN0
set_error => comb_proc~0.IN1
error <= int_dout.DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_error_reg:i3_rx_error_reg
clk => int_dout.CLK
reset => sync_proc~0.IN0
clr_error_n => sync_proc~0.IN1
enable_error => comb_proc~0.IN0
set_error => comb_proc~0.IN1
error <= int_dout.DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_break_cnt:i_rx_break_cnt
reset => space_bit_count[4].OUTPUTSELECT
reset => space_bit_count[3].OUTPUTSELECT
reset => space_bit_count[2].OUTPUTSELECT
reset => space_bit_count[1].OUTPUTSELECT
reset => space_bit_count[0].OUTPUTSELECT
reset => term_count_val[4].OUTPUTSELECT
reset => term_count_val[3].OUTPUTSELECT
reset => term_count_val[2].OUTPUTSELECT
reset => term_count_val[1].OUTPUTSELECT
reset => term_count_val[0].OUTPUTSELECT
reset => space_sample_count[0].ACLR
reset => space_sample_count[1].ACLR
reset => space_sample_count[2].ACLR
reset => space_sample_count[3].ACLR
reset => space_sample_count[4].ACLR
reset => space_sample_count[5].ACLR
reset => space_sample_count[6].ACLR
reset => space_sample_count[7].ACLR
reset => space_sample_count[8].ACLR
reset => space_sample_count[9].ACLR
reset => space_sample_count[10].ACLR
clk => space_sample_count[0].CLK
clk => space_sample_count[1].CLK
clk => space_sample_count[2].CLK
clk => space_sample_count[3].CLK
clk => space_sample_count[4].CLK
clk => space_sample_count[5].CLK
clk => space_sample_count[6].CLK
clk => space_sample_count[7].CLK
clk => space_sample_count[8].CLK
clk => space_sample_count[9].CLK
clk => space_sample_count[10].CLK
sclr => space_sample_count~11.OUTPUTSELECT
sclr => space_sample_count~12.OUTPUTSELECT
sclr => space_sample_count~13.OUTPUTSELECT
sclr => space_sample_count~14.OUTPUTSELECT
sclr => space_sample_count~15.OUTPUTSELECT
sclr => space_sample_count~16.OUTPUTSELECT
sclr => space_sample_count~17.OUTPUTSELECT
sclr => space_sample_count~18.OUTPUTSELECT
sclr => space_sample_count~19.OUTPUTSELECT
sclr => space_sample_count~20.OUTPUTSELECT
sclr => space_sample_count~21.OUTPUTSELECT
parity_en => Mux3.IN2
parity_en => Mux0.IN3
parity_en => Mux3.IN3
parity_en => Mux2.IN3
parity_en => Mux4.IN3
parity_en => Mux7.IN2
parity_en => Mux6.IN3
parity_en => Mux7.IN3
parity_en => Mux5.IN3
parity_en => Mux1.IN3
parity_en => Mux6.IN2
parity_en => Mux2.IN2
parity_en => Mux7.IN0
parity_en => Mux7.IN1
parity_en => Mux3.IN0
parity_en => Mux3.IN1
ce => space_sample_count_proc~0.IN1
l1 => Mux0.IN5
l1 => Mux1.IN5
l1 => Mux2.IN5
l1 => Mux3.IN5
l1 => Mux4.IN5
l1 => Mux5.IN5
l1 => Mux6.IN5
l1 => Mux7.IN5
l2 => Mux0.IN4
l2 => Mux1.IN4
l2 => Mux2.IN4
l2 => Mux3.IN4
l2 => Mux4.IN4
l2 => Mux5.IN4
l2 => Mux6.IN4
l2 => Mux7.IN4
s1 => Mux8.IN5
s1 => Mux9.IN5
s1 => Mux10.IN5
s1 => Mux11.IN5
s1 => Mux12.IN5
s2 => Mux8.IN4
s2 => Mux9.IN4
s2 => Mux10.IN4
s2 => Mux11.IN4
s2 => Mux12.IN4
b1 => Mux13.IN2
b1 => Mux14.IN2
b1 => Mux15.IN2
b1 => Mux16.IN2
b1 => Mux17.IN2
b2 => Mux13.IN1
b2 => Mux14.IN1
b2 => Mux15.IN1
b2 => Mux16.IN1
b2 => Mux17.IN1
tc <= Equal0.DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_sync_stat:i_rx_sync_stat
clk => int_dout.CLK
clr => sync_proc~0.IN0
sclr => mux_dout.OUTPUTSELECT
proc_ce => sync_proc~0.IN1
sync_ce => mux_dout~0.OUTPUTSELECT
syncrdy <= int_dout.DB_MAX_OUTPUT_PORT_TYPE


|A8251|tx:i_tx
reset => tx_shift_reg:i_tx_shift_reg.reset
reset => tx_par_gen:i_tx_par_gen.reset
reset => tx_cntrl:i_tx_cntrl.reset
txclk => tx_shift_reg:i_tx_shift_reg.txclk
txclk => tx_par_gen:i_tx_par_gen.txclk
txclk => tx_cntrl:i_tx_cntrl.txclk
tx_resetn => tx_shift_reg:i_tx_shift_reg.sync_rst
tx_resetn => tx_cntrl:i_tx_cntrl.tx_resetn
parity_en => tx_cntrl:i_tx_cntrl.parity_en
parity_even => tx_par_gen:i_tx_par_gen.parity_even
s1 => tx_cntrl:i_tx_cntrl.s1
s2 => tx_cntrl:i_tx_cntrl.s2
b1 => tx_cntrl:i_tx_cntrl.b1
b2 => tx_cntrl:i_tx_cntrl.b2
l1 => tx_data_mux:i_tx_data_mux.l1
l1 => tx_cntrl:i_tx_cntrl.l1
l2 => tx_data_mux:i_tx_data_mux.l2
l2 => tx_cntrl:i_tx_cntrl.l2
tx_en => tx_cntrl:i_tx_cntrl.tx_en
cts => tx_cntrl:i_tx_cntrl.cts
break_en => tx_line_mux:i_tx_line_mux.break_en
tx_fifo_ef_n => tx_cntrl:i_tx_cntrl.tx_fifo_ef_n
txdin[0] => tx_data_mux:i_tx_data_mux.di[0]