a8251.hier_info

8251芯片功能的vhdl描述

|A8251|proc:i_procintf|proc_sync_reg:I_proc_sync_reg1
clk => int_dout[0].CLK
clk => int_dout[1].CLK
clk => int_dout[2].CLK
clk => int_dout[3].CLK
clk => int_dout[4].CLK
clk => int_dout[5].CLK
clk => int_dout[6].CLK
clk => int_dout[7].CLK
clr => int_dout[0].ACLR
clr => int_dout[1].ACLR
clr => int_dout[2].ACLR
clr => int_dout[3].ACLR
clr => int_dout[4].ACLR
clr => int_dout[5].ACLR
clr => int_dout[6].ACLR
clr => int_dout[7].ACLR
sclr => mux_dout[7].OUTPUTSELECT
sclr => mux_dout[6].OUTPUTSELECT
sclr => mux_dout[5].OUTPUTSELECT
sclr => mux_dout[4].OUTPUTSELECT
sclr => mux_dout[3].OUTPUTSELECT
sclr => mux_dout[2].OUTPUTSELECT
sclr => mux_dout[1].OUTPUTSELECT
sclr => mux_dout[0].OUTPUTSELECT
ce => mux_dout~0.OUTPUTSELECT
ce => mux_dout~1.OUTPUTSELECT
ce => mux_dout~2.OUTPUTSELECT
ce => mux_dout~3.OUTPUTSELECT
ce => mux_dout~4.OUTPUTSELECT
ce => mux_dout~5.OUTPUTSELECT
ce => mux_dout~6.OUTPUTSELECT
ce => mux_dout~7.OUTPUTSELECT
d[0] => mux_dout~7.DATAB
d[1] => mux_dout~6.DATAB
d[2] => mux_dout~5.DATAB
d[3] => mux_dout~4.DATAB
d[4] => mux_dout~3.DATAB
d[5] => mux_dout~2.DATAB
d[6] => mux_dout~1.DATAB
d[7] => mux_dout~0.DATAB
q[0] <= int_dout[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= int_dout[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= int_dout[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= int_dout[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= int_dout[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= int_dout[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= int_dout[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= int_dout[7].DB_MAX_OUTPUT_PORT_TYPE


|A8251|proc:i_procintf|proc_sync_reg:I_proc_sync_reg2
clk => int_dout[0].CLK
clk => int_dout[1].CLK
clk => int_dout[2].CLK
clk => int_dout[3].CLK
clk => int_dout[4].CLK
clk => int_dout[5].CLK
clk => int_dout[6].CLK
clk => int_dout[7].CLK
clr => int_dout[0].ACLR
clr => int_dout[1].ACLR
clr => int_dout[2].ACLR
clr => int_dout[3].ACLR
clr => int_dout[4].ACLR
clr => int_dout[5].ACLR
clr => int_dout[6].ACLR
clr => int_dout[7].ACLR
sclr => mux_dout[7].OUTPUTSELECT
sclr => mux_dout[6].OUTPUTSELECT
sclr => mux_dout[5].OUTPUTSELECT
sclr => mux_dout[4].OUTPUTSELECT
sclr => mux_dout[3].OUTPUTSELECT
sclr => mux_dout[2].OUTPUTSELECT
sclr => mux_dout[1].OUTPUTSELECT
sclr => mux_dout[0].OUTPUTSELECT
ce => mux_dout~0.OUTPUTSELECT
ce => mux_dout~1.OUTPUTSELECT
ce => mux_dout~2.OUTPUTSELECT
ce => mux_dout~3.OUTPUTSELECT
ce => mux_dout~4.OUTPUTSELECT
ce => mux_dout~5.OUTPUTSELECT
ce => mux_dout~6.OUTPUTSELECT
ce => mux_dout~7.OUTPUTSELECT
d[0] => mux_dout~7.DATAB
d[1] => mux_dout~6.DATAB
d[2] => mux_dout~5.DATAB
d[3] => mux_dout~4.DATAB
d[4] => mux_dout~3.DATAB
d[5] => mux_dout~2.DATAB
d[6] => mux_dout~1.DATAB
d[7] => mux_dout~0.DATAB
q[0] <= int_dout[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= int_dout[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= int_dout[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= int_dout[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= int_dout[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= int_dout[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= int_dout[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= int_dout[7].DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx
reset => rx_sync_stat:i_rx_sync_stat.clr
reset => rx_break_cnt:i_rx_break_cnt.reset
reset => rx_error_reg:i3_rx_error_reg.reset
reset => rx_error_reg:i2_rx_error_reg.reset
reset => rx_error_reg:i1_rx_error_reg.reset
reset => rx_data_cnt:i_rx_data_cnt.reset
reset => rx_data_reg:i_rx_data_reg.clr
reset => rx_shift_reg:i_rx_shift_reg.reset
reset => rx_det_cntrl:i_rx_det_cntrl.reset
reset => rx_cntrl:i_rx_cntrl.reset
reset => rx_ready_reg:I_rx_ready_reg.clr
mr => rx_sync_stat:i_rx_sync_stat.sclr
mr => rx_data_reg:i_rx_data_reg.sclr
mr => rx_shift_reg:i_rx_shift_reg.sclr
mr => rx_det_cntrl:i_rx_det_cntrl.mr
mr => rx_cntrl:i_rx_cntrl.mr
mr => rx_ready_reg:I_rx_ready_reg.sclr
rx_en => rx_break_cnt:i_rx_break_cnt.ce
rx_en => rx_cntrl:i_rx_cntrl.rx_en
rxclk => rx_sync_stat:i_rx_sync_stat.clk
rxclk => rx_break_cnt:i_rx_break_cnt.clk
rxclk => rx_error_reg:i3_rx_error_reg.clk
rxclk => rx_error_reg:i2_rx_error_reg.clk
rxclk => rx_error_reg:i1_rx_error_reg.clk
rxclk => rx_data_cnt:i_rx_data_cnt.clk
rxclk => rx_data_reg:i_rx_data_reg.clk
rxclk => rx_shift_reg:i_rx_shift_reg.clock
rxclk => rx_det_cntrl:i_rx_det_cntrl.rxclk
rxclk => rx_cntrl:i_rx_cntrl.rxclk
rxclk => rx_ready_reg:I_rx_ready_reg.clk
rxdata => rx_break_cnt:i_rx_break_cnt.sclr
rxdata => rx_shift_reg:i_rx_shift_reg.sli
rxdata => rx_cntrl:i_rx_cntrl.rxdata
sts_read => rx_sync_stat:i_rx_sync_stat.proc_ce
mode_cmplt => rx_cntrl:i_rx_cntrl.mode_cmplt
hunt => rx_det_cntrl:i_rx_det_cntrl.hunt
hunt => rx_cntrl:i_rx_cntrl.hunt
scs => rx_break_cnt:i_rx_break_cnt.s2
scs => rx_det_cntrl:i_rx_det_cntrl.scs
esd => rx_break_cnt:i_rx_break_cnt.s1
esd => rx_det_cntrl:i_rx_det_cntrl.esd
esd => rx_cntrl:i_rx_cntrl.esd
ExtSyncD => rx_det_cntrl:i_rx_det_cntrl.ExtSyncD
er => rx_error_reg:i3_rx_error_reg.clr_error_n
er => rx_error_reg:i2_rx_error_reg.clr_error_n
er => rx_error_reg:i1_rx_error_reg.clr_error_n
er => rx_ready_reg:I_rx_ready_reg.error_resetn
b1 => rx_break_cnt:i_rx_break_cnt.b1
b1 => rx_det_cntrl:i_rx_det_cntrl.b1
b1 => rx_cntrl:i_rx_cntrl.b1
b1 => syn_brk~0.IN0
b2 => rx_break_cnt:i_rx_break_cnt.b2
b2 => rx_det_cntrl:i_rx_det_cntrl.b2
b2 => rx_cntrl:i_rx_cntrl.b2
b2 => syn_brk~0.IN1
l1 => rx_break_cnt:i_rx_break_cnt.l1
l1 => rx_data_cnt:i_rx_data_cnt.l1
l1 => rx_data_reg:i_rx_data_reg.l1
l1 => rx_shift_reg:i_rx_shift_reg.l1
l1 => rx_sync_comp:i_rx_sync_comp.l1
l2 => rx_break_cnt:i_rx_break_cnt.l2
l2 => rx_data_cnt:i_rx_data_cnt.l2
l2 => rx_data_reg:i_rx_data_reg.l2
l2 => rx_shift_reg:i_rx_shift_reg.l2
l2 => rx_sync_comp:i_rx_sync_comp.l2
parity_en => rx_break_cnt:i_rx_break_cnt.parity_en
parity_en => rx_par_tree:i_rx_par_tree.parity_en
parity_en => rx_data_cnt:i_rx_data_cnt.parity_en
parity_en => rx_shift_reg:i_rx_shift_reg.parity_en
parity_en => rx_cntrl:i_rx_cntrl.parity_en
even_parity => rx_par_tree:i_rx_par_tree.even_parity
s1 => rx_cntrl:i_rx_cntrl.s1
s2 => rx_cntrl:i_rx_cntrl.s2
rx_read => rx_ready_reg:I_rx_ready_reg.rx_rdy_clr
sync_char1[0] => rx_sync_comp:i_rx_sync_comp.sync_char1[0]
sync_char1[1] => rx_sync_comp:i_rx_sync_comp.sync_char1[1]
sync_char1[2] => rx_sync_comp:i_rx_sync_comp.sync_char1[2]
sync_char1[3] => rx_sync_comp:i_rx_sync_comp.sync_char1[3]
sync_char1[4] => rx_sync_comp:i_rx_sync_comp.sync_char1[4]
sync_char1[5] => rx_sync_comp:i_rx_sync_comp.sync_char1[5]
sync_char1[6] => rx_sync_comp:i_rx_sync_comp.sync_char1[6]
sync_char1[7] => rx_sync_comp:i_rx_sync_comp.sync_char1[7]
sync_char2[0] => rx_sync_comp:i_rx_sync_comp.sync_char2[0]
sync_char2[1] => rx_sync_comp:i_rx_sync_comp.sync_char2[1]
sync_char2[2] => rx_sync_comp:i_rx_sync_comp.sync_char2[2]
sync_char2[3] => rx_sync_comp:i_rx_sync_comp.sync_char2[3]
sync_char2[4] => rx_sync_comp:i_rx_sync_comp.sync_char2[4]
sync_char2[5] => rx_sync_comp:i_rx_sync_comp.sync_char2[5]
sync_char2[6] => rx_sync_comp:i_rx_sync_comp.sync_char2[6]
sync_char2[7] => rx_sync_comp:i_rx_sync_comp.sync_char2[7]
fe <= rx_error_reg:i3_rx_error_reg.error
pe <= rx_error_reg:i1_rx_error_reg.error
oe <= rx_error_reg:i2_rx_error_reg.error
syn_brk <= syn_brk~1.DB_MAX_OUTPUT_PORT_TYPE
rxrdy <= rx_ready_reg:I_rx_ready_reg.rxrdy
rxreg[0] <= rx_data_reg:i_rx_data_reg.q[0]
rxreg[1] <= rx_data_reg:i_rx_data_reg.q[1]
rxreg[2] <= rx_data_reg:i_rx_data_reg.q[2]
rxreg[3] <= rx_data_reg:i_rx_data_reg.q[3]
rxreg[4] <= rx_data_reg:i_rx_data_reg.q[4]
rxreg[5] <= rx_data_reg:i_rx_data_reg.q[5]
rxreg[6] <= rx_data_reg:i_rx_data_reg.q[6]
rxreg[7] <= rx_data_reg:i_rx_data_reg.q[7]


|A8251|rx:i_rx|rx_ready_reg:I_rx_ready_reg
clk => int_rxrdy.CLK
clr => reg_proc~0.IN0
clr => stat_proc~0.IN1
sclr => dec_rxrdy.OUTPUTSELECT
rx_rdy_clr => reg_proc~0.IN1
rx_rdy_set => dec_rxrdy~0.OUTPUTSELECT
error_resetn => frame_clr.CLK
frame_err => frame_clr.DATAIN
rxrdy <= int_rxrdy.DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_cntrl:i_rx_cntrl
reset => rx_cntrl_cnt:i_rx_cntrl_cnt.clr
reset => rx_cntrl_sm:i_rx_cntrlsm.reset
mr => rx_cntrl_sm:i_rx_cntrlsm.mr
rx_en => rx_cntrl_sm:i_rx_cntrlsm.rx_en
rxclk => rx_cntrl_cnt:i_rx_cntrl_cnt.clk
rxclk => rx_cntrl_sm:i_rx_cntrlsm.rxclk
mode_cmplt => rx_cntrl_sm:i_rx_cntrlsm.mode_cmplt
syndet => rx_cntrl_sm:i_rx_cntrlsm.syndet
esd => rx_cntrl_sm:i_rx_cntrlsm.esd
hunt => rx_cntrl_sm:i_rx_cntrlsm.hunt
rxdata => rx_cntrl_sm:i_rx_cntrlsm.rxdata
b1 => rx_cntrl_cnt:i_rx_cntrl_cnt.mode
b1 => rx_cntrl_sm:i_rx_cntrlsm.b1
b2 => rx_cntrl_sm:i_rx_cntrlsm.b2
parity_en => rx_cntrl_sm:i_rx_cntrlsm.parity_en
s1 => rx_cntrl_sm:i_rx_cntrlsm.s1
s2 => rx_cntrl_sm:i_rx_cntrlsm.s2
rxrdy => rx_cntrl_sm:i_rx_cntrlsm.rxrdy
data_tc => rx_cntrl_sm:i_rx_cntrlsm.data_tc
dat_clr <= rx_cntrl_sm:i_rx_cntrlsm.dat_clr
shift_en <= rx_cntrl_sm:i_rx_cntrlsm.shift_en
frame_err <= rx_cntrl_sm:i_rx_cntrlsm.frame_err
overrun_err <= rx_cntrl_sm:i_rx_cntrlsm.overrun_err
tran_en <= rx_cntrl_sm:i_rx_cntrlsm.tran_en


|A8251|rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_sm:i_rx_cntrlsm
reset => state~1.IN1
rxclk => state~0.IN1
mr => next_state.idle.OUTPUTSELECT
mr => next_state.sync_det.OUTPUTSELECT
mr => next_state.wait_sync.OUTPUTSELECT
mr => next_state.sync_data.OUTPUTSELECT
mr => next_state.sync_parity.OUTPUTSELECT
mr => next_state.wait_start.OUTPUTSELECT
mr => next_state.false_start_det.OUTPUTSELECT
mr => next_state.wait_data.OUTPUTSELECT
mr => next_state.sample_data.OUTPUTSELECT
mr => next_state.wait_parity.OUTPUTSELECT
mr => next_state.sample_parity.OUTPUTSELECT
mr => next_state.wait_stop1.OUTPUTSELECT
mr => next_state.sample_stop1.OUTPUTSELECT
mr => next_state.wait_stop2.OUTPUTSELECT
mr => next_state.sample_stop2.OUTPUTSELECT
mr => next_state.db1_data.OUTPUTSELECT
mr => next_state.db1_parity.OUTPUTSELECT
mr => next_state.db1_stop1.OUTPUTSELECT
mr => next_state.db1_stop2.OUTPUTSELECT
mr => shift_en~0.OUTPUTSELECT
mr => cnt_en~0.OUTPUTSELECT
mr => clr_cnt~2.OUTPUTSELECT
mr => dat_clr~4.OUTPUTSELECT
mr => frame_err~0.OUTPUTSELECT
mr => overrun_err~6.OUTPUTSELECT
mr => tran_en~5.OUTPUTSELECT
rx_en => statetran~0.IN1
rx_en => tran_en~0.DATAA
rx_en => overrun_err~1.DATAB
rx_en => tran_en~3.DATAA
mode_cmplt => next_state~0.OUTPUTSELECT
mode_cmplt => dat_clr~0.OUTPUTSELECT
mode_cmplt => next_state~12.DATAB
syndet => statetran~3.IN0
syndet => next_state~8.DATAA
syndet => next_state~7.DATAA
esd => statetran~3.IN1
hunt => tran_en~2.OUTPUTSELECT
hunt => dat_clr~1.OUTPUTSELECT
hunt => overrun_err~4.OUTPUTSELECT
hunt => Selector4.IN4
hunt => next_state~10.OUTPUTSELECT
hunt => next_state~11.OUTPUTSELECT
hunt => tran_en~3.OUTPUTSELECT
hunt => overrun_err~5.OUTPUTSELECT
hunt => dat_clr~2.OUTPUTSELECT
hunt => Selector4.IN5
hunt => Selector5.IN4
rxdata => Selector6.IN8
rxdata => next_state~3.OUTPUTSELECT
rxdata => clr_cnt~0.OUTPUTSELECT
rxdata => Selector0.IN1
rxdata => statetran~0.IN0
tc_half => statetran~1.IN0
tc_half => clr_cnt~0.DATAA
tc_half => next_state~3.DATAA
tc_full => next_state~15.DATAB
tc_full => Selector3.IN6
tc_full => next_state~16.DATAB
tc_full => Selector3.IN7
tc_full => next_state~17.DATAB
tc_full => Selector3.IN8
tc_full => statetran~2.IN1
tc_full => Selector10.IN2
tc_full => Selector9.IN1
tc_full => Selector8.IN2
b1 => Equal0.IN1
b1 => Equal1.IN1
b2 => Equal0.IN0
b2 => Equal1.IN0
data_tc => Selector14.IN7
data_tc => Selector14.IN8
data_tc => next_state~5.OUTPUTSELECT
data_tc => next_state~6.OUTPUTSELECT
data_tc => tran_en~1.OUTPUTSELECT
data_tc => dat_clr~1.DATAA
data_tc => overrun_err~3.OUTPUTSELECT
data_tc => next_state~9.OUTPUTSELECT
data_tc => Selector12.IN2
data_tc => Selector8.IN3
parity_en => next_state~5.DATAB
parity_en => tran_en~0.OUTPUTSELECT
parity_en => overrun_err~2.OUTPUTSELECT
parity_en => next_state~6.DATAB
parity_en => next_state~9.DATAB
s1 => Equal2.IN0
s1 => Equal3.IN1
s2 => Equal2.IN1
s2 => Equal3.IN0
rxrdy => overrun_err~0.DATAB
rxrdy => Selector1.IN6
rxrdy => Selector1.IN7
rxrdy => overrun_err~1.OUTPUTSELECT
rxrdy => dat_clr~2.DATAA
shift_en <= shift_en~0.DB_MAX_OUTPUT_PORT_TYPE
dat_clr <= dat_clr~4.DB_MAX_OUTPUT_PORT_TYPE
cnt_en <= cnt_en~0.DB_MAX_OUTPUT_PORT_TYPE
clr_cnt <= clr_cnt~2.DB_MAX_OUTPUT_PORT_TYPE
frame_err <= frame_err~0.DB_MAX_OUTPUT_PORT_TYPE
overrun_err <= overrun_err~6.DB_MAX_OUTPUT_PORT_TYPE
tran_en <= tran_en~5.DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_cntrl:i_rx_cntrl|rx_cntrl_cnt:i_rx_cntrl_cnt
clk => int_dout[0].CLK
clk => int_dout[1].CLK
clk => int_dout[2].CLK
clk => int_dout[3].CLK
clk => int_dout[4].CLK
clk => int_dout[5].CLK
clr => int_dout[0].ACLR
clr => int_dout[1].ACLR
clr => int_dout[2].ACLR
clr => int_dout[3].ACLR
clr => int_dout[4].ACLR
clr => int_dout[5].ACLR
sclr => mux_dout[5].OUTPUTSELECT
sclr => mux_dout[4].OUTPUTSELECT
sclr => mux_dout[3].OUTPUTSELECT
sclr => mux_dout[2].OUTPUTSELECT
sclr => mux_dout[1].OUTPUTSELECT
sclr => mux_dout[0].OUTPUTSELECT
ce => tc1~0.IN0
ce => tc2~0.IN0
ce => mux_dout~0.OUTPUTSELECT
ce => mux_dout~1.OUTPUTSELECT
ce => mux_dout~2.OUTPUTSELECT
ce => mux_dout~3.OUTPUTSELECT
ce => mux_dout~4.OUTPUTSELECT
ce => mux_dout~5.OUTPUTSELECT
mode => int_tc1.OUTPUTSELECT
mode => int_tc2.OUTPUTSELECT
tc1 <= tc1~0.DB_MAX_OUTPUT_PORT_TYPE
tc2 <= tc2~0.DB_MAX_OUTPUT_PORT_TYPE


|A8251|rx:i_rx|rx_det_cntrl:i_rx_det_cntrl
reset => state~1.IN1
rxclk => state~0.IN1
mr => next_state.idle.OUTPUTSELECT
mr => next_state.hunt_sync.OUTPUTSELECT
mr => next_state.find_sync2.OUTPUTSELECT
mr => next_state.synced1.OUTPUTSELECT
mr => next_state.synced2.OUTPUTSELECT
mr => int_syncdet~3.OUTPUTSELECT
mr => en_sync~2.OUTPUTSELECT
mr => sync_ce~1.OUTPUTSELECT
mr => en_cnt~1.OUTPUTSELECT
mr => clr_cnt~2.OUTPUTSELECT
scs => statetran~2.IN0
scs => statetran~3.IN0
esd => next_state~10.OUTPUTSELECT
esd => next_state~11.OUTPUTSELECT
esd => next_state~12.OUTPUTSELECT
esd => next_state~13.OUTPUTSELECT
esd => next_state~14.OUTPUTSELECT
esd => int_syncdet~2.OUTPUTSELECT
esd => en_sync~1.OUTPUTSELECT
esd => sync_ce~0.OUTPUTSELECT
esd => en_cnt~0.OUTPUTSELECT
esd => clr_cnt~1.OUTPUTSELECT
ExtSyncD => int_syncdet~2.DATAB
sync1_eq => statetran~2.IN1
sync1_eq => statetran~3.IN1
sync2_eq => statetran~4.IN0
sync2_eq => statetran~8.IN0
sync2_eq => statetran~5.IN0
hunt => statetran~0.IN0
hunt => int_syncdet~0.OUTPUTSELECT