a8251.hier_info

8251芯片功能的vhdl描述

|A8251
clk => proc:i_procintf.clk
reset => tx_fifo:i_tx_fifo.rst_n
reset => tx:i_tx.reset
reset => rx:i_rx.reset
reset => proc:i_procintf.clr
reset => Wr_Ext:i_Wr_Ext.RESET
reset => AddrLatch:i_AddrSync.RESET
reset => DataLatch:i_DataSync.RESET
nWR => proc:i_procintf.nWR
nWR => Wr_Ext:i_Wr_Ext.nWR
nWR => AddrLatch:i_AddrSync.nWR
nWR => DataLatch:i_DataSync.nWR
nRD => proc:i_procintf.nRD
nRD => nEN~0.IN1
nCS => proc:i_procintf.nCS
nCS => Wr_Ext:i_Wr_Ext.nCS
nCS => AddrLatch:i_AddrSync.nCS
nCS => DataLatch:i_DataSync.nCS
nCS => nEN~0.IN0
CnD => proc:i_procintf.CnD
CnD => AddrLatch:i_AddrSync.CnD
CnD => dout_mux:i_dout_mux.CnD
nDSR => dout_mux:i_dout_mux.status_data[7]
nCTS => tx:i_tx.cts
nCTS => int_txrdy~0.IN1
ExtSyncD => rx:i_rx.ExtSyncD
nTxC => tx_fifo:i_tx_fifo.rd_clk
nTxC => tx:i_tx.txclk
nTxC => proc:i_procintf.txclk
nRxC => rx:i_rx.rxclk
nRxC => proc:i_procintf.rxclk
rxd => rx:i_rx.rxdata
din[0] => DataLatch:i_DataSync.DIN[0]
din[1] => DataLatch:i_DataSync.DIN[1]
din[2] => DataLatch:i_DataSync.DIN[2]
din[3] => DataLatch:i_DataSync.DIN[3]
din[4] => DataLatch:i_DataSync.DIN[4]
din[5] => DataLatch:i_DataSync.DIN[5]
din[6] => DataLatch:i_DataSync.DIN[6]
din[7] => DataLatch:i_DataSync.DIN[7]
txd <= tx:i_tx.txdata
txrdy <= int_txrdy~1.DB_MAX_OUTPUT_PORT_TYPE
txempty <= int_txempty~0.DB_MAX_OUTPUT_PORT_TYPE
rxrdy <= rx:i_rx.rxrdy
nDTR <= proc:i_procintf.nDTR
nRTS <= proc:i_procintf.nRTS
syn_brk <= rx:i_rx.syn_brk
nEN <= nEN~0.DB_MAX_OUTPUT_PORT_TYPE
dout[0] <= dout_mux:i_dout_mux.dout[0]
dout[1] <= dout_mux:i_dout_mux.dout[1]
dout[2] <= dout_mux:i_dout_mux.dout[2]
dout[3] <= dout_mux:i_dout_mux.dout[3]
dout[4] <= dout_mux:i_dout_mux.dout[4]
dout[5] <= dout_mux:i_dout_mux.dout[5]
dout[6] <= dout_mux:i_dout_mux.dout[6]
dout[7] <= dout_mux:i_dout_mux.dout[7]


|A8251|dout_mux:i_dout_mux
CnD => dout~0.OUTPUTSELECT
CnD => dout~1.OUTPUTSELECT
CnD => dout~2.OUTPUTSELECT
CnD => dout~3.OUTPUTSELECT
CnD => dout~4.OUTPUTSELECT
CnD => dout~5.OUTPUTSELECT
CnD => dout~6.OUTPUTSELECT
CnD => dout~7.OUTPUTSELECT
rx_data[0] => dout~7.DATAB
rx_data[1] => dout~6.DATAB
rx_data[2] => dout~5.DATAB
rx_data[3] => dout~4.DATAB
rx_data[4] => dout~3.DATAB
rx_data[5] => dout~2.DATAB
rx_data[6] => dout~1.DATAB
rx_data[7] => dout~0.DATAB
status_data[0] => dout~7.DATAA
status_data[1] => dout~6.DATAA
status_data[2] => dout~5.DATAA
status_data[3] => dout~4.DATAA
status_data[4] => dout~3.DATAA
status_data[5] => dout~2.DATAA
status_data[6] => dout~1.DATAA
status_data[7] => dout~0.DATAA
dout[0] <= dout~7.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout~6.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout~5.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout~4.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout~3.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout~2.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout~1.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout~0.DB_MAX_OUTPUT_PORT_TYPE


|A8251|DataLatch:i_DataSync
RESET => LatchedData[0]$latch.ACLR
RESET => LatchedData[1]$latch.ACLR
RESET => LatchedData[2]$latch.ACLR
RESET => LatchedData[3]$latch.ACLR
RESET => LatchedData[4]$latch.ACLR
RESET => LatchedData[5]$latch.ACLR
RESET => LatchedData[6]$latch.ACLR
RESET => LatchedData[7]$latch.ACLR
DIN[0] => LatchedData[0]$latch.DATAIN
DIN[1] => LatchedData[1]$latch.DATAIN
DIN[2] => LatchedData[2]$latch.DATAIN
DIN[3] => LatchedData[3]$latch.DATAIN
DIN[4] => LatchedData[4]$latch.DATAIN
DIN[5] => LatchedData[5]$latch.DATAIN
DIN[6] => LatchedData[6]$latch.DATAIN
DIN[7] => LatchedData[7]$latch.DATAIN
nWR => LatchProc~0.IN1
nCS => LatchProc~0.IN0
LatchedData[0] <= LatchedData[0]$latch
LatchedData[1] <= LatchedData[1]$latch
LatchedData[2] <= LatchedData[2]$latch
LatchedData[3] <= LatchedData[3]$latch
LatchedData[4] <= LatchedData[4]$latch
LatchedData[5] <= LatchedData[5]$latch
LatchedData[6] <= LatchedData[6]$latch
LatchedData[7] <= LatchedData[7]$latch


|A8251|AddrLatch:i_AddrSync
RESET => LatchedAddr$latch.ACLR
CnD => LatchedAddr$latch.DATAIN
nWR => LatchProc~0.IN1
nCS => LatchProc~0.IN0
LatchedAddr <= LatchedAddr$latch


|A8251|Wr_Ext:i_Wr_Ext
RESET => WriteExtProc~0.IN0
nCS => WriteExtProc~1.IN1
nWR => ext_nWR~reg0.CLK
cycle_rec => WriteExtProc~0.IN1
ext_nWR <= ext_nWR~reg0


|A8251|proc:i_procintf
ext_nWR => proc_dec:I_proc_dec.ext_nWR
nWR => proc_dec:I_proc_dec.nWR
nRD => proc_dec:I_proc_dec.nRD
ext_CnD => proc_dec:I_proc_dec.ext_CnD
CnD => proc_dec:I_proc_dec.CnD
nCS => proc_dec:I_proc_dec.nCS
clr => proc_sync_reg:I_proc_sync_reg2.clr
clr => proc_sync_reg:I_proc_sync_reg1.clr
clr => proc_sm:I_proc_sm.reset
clr => proc_dec:I_proc_dec.reset
clr => proc_mode_reg:I_proc_mode_reg.clr
clr => proc_cmd_reg:I_proc_cmd_reg.clr
clk => proc_sync_reg:I_proc_sync_reg2.clk
clk => proc_sync_reg:I_proc_sync_reg1.clk
clk => proc_sm:I_proc_sm.clk
clk => proc_dec:I_proc_dec.clk
clk => proc_mode_reg:I_proc_mode_reg.clk
clk => proc_cmd_reg:I_proc_cmd_reg.mclk
d[0] => proc_sync_reg:I_proc_sync_reg2.d[0]
d[0] => proc_sync_reg:I_proc_sync_reg1.d[0]
d[0] => proc_mode_reg:I_proc_mode_reg.d[0]
d[0] => proc_cmd_reg:I_proc_cmd_reg.din[0]
d[1] => proc_sync_reg:I_proc_sync_reg2.d[1]
d[1] => proc_sync_reg:I_proc_sync_reg1.d[1]
d[1] => proc_mode_reg:I_proc_mode_reg.d[1]
d[1] => proc_cmd_reg:I_proc_cmd_reg.din[1]
d[2] => proc_sync_reg:I_proc_sync_reg2.d[2]
d[2] => proc_sync_reg:I_proc_sync_reg1.d[2]
d[2] => proc_mode_reg:I_proc_mode_reg.d[2]
d[2] => proc_cmd_reg:I_proc_cmd_reg.din[2]
d[3] => proc_sync_reg:I_proc_sync_reg2.d[3]
d[3] => proc_sync_reg:I_proc_sync_reg1.d[3]
d[3] => proc_mode_reg:I_proc_mode_reg.d[3]
d[3] => proc_cmd_reg:I_proc_cmd_reg.din[3]
d[4] => proc_sync_reg:I_proc_sync_reg2.d[4]
d[4] => proc_sync_reg:I_proc_sync_reg1.d[4]
d[4] => proc_mode_reg:I_proc_mode_reg.d[4]
d[4] => proc_cmd_reg:I_proc_cmd_reg.din[4]
d[5] => proc_sync_reg:I_proc_sync_reg2.d[5]
d[5] => proc_sync_reg:I_proc_sync_reg1.d[5]
d[5] => proc_mode_reg:I_proc_mode_reg.d[5]
d[5] => proc_cmd_reg:I_proc_cmd_reg.din[5]
d[6] => proc_sync_reg:I_proc_sync_reg2.d[6]
d[6] => proc_sync_reg:I_proc_sync_reg1.d[6]
d[6] => proc_mode_reg:I_proc_mode_reg.d[6]
d[6] => proc_cmd_reg:I_proc_cmd_reg.din[6]
d[7] => proc_sync_reg:I_proc_sync_reg2.d[7]
d[7] => proc_sync_reg:I_proc_sync_reg1.d[7]
d[7] => proc_mode_reg:I_proc_mode_reg.d[7]
d[7] => proc_cmd_reg:I_proc_cmd_reg.din[7]
rxclk => proc_cmd_reg:I_proc_cmd_reg.rxclk
txclk => proc_cmd_reg:I_proc_cmd_reg.txclk
cycle_rec <= proc_dec:I_proc_dec.cycle_rec
hunt <= proc_cmd_reg:I_proc_cmd_reg.hunt
error_resetn <= proc_cmd_reg:I_proc_cmd_reg.error_resetn
rx_resetn <= proc_cmd_reg:I_proc_cmd_reg.rx_resetn
tx_resetn <= proc_cmd_reg:I_proc_cmd_reg.tx_resetn
nRTS <= proc_cmd_reg:I_proc_cmd_reg.nRTS
nDTR <= proc_cmd_reg:I_proc_cmd_reg.nDTR
rx_enable <= proc_cmd_reg:I_proc_cmd_reg.rx_enable
tx_enable <= proc_cmd_reg:I_proc_cmd_reg.tx_enable
break_enable <= proc_cmd_reg:I_proc_cmd_reg.break_enable
mode_cmplt <= proc_sm:I_proc_sm.init_done
sts_read <= proc_dec:I_proc_dec.sts_read
tx_fifo_wr_n <= proc_dec:I_proc_dec.tx_fifo_wr_n
rx_read <= proc_dec:I_proc_dec.rx_read
mode_out[0] <= proc_mode_reg:I_proc_mode_reg.q[0]
mode_out[1] <= proc_mode_reg:I_proc_mode_reg.q[1]
mode_out[2] <= proc_mode_reg:I_proc_mode_reg.q[2]
mode_out[3] <= proc_mode_reg:I_proc_mode_reg.q[3]
mode_out[4] <= proc_mode_reg:I_proc_mode_reg.q[4]
mode_out[5] <= proc_mode_reg:I_proc_mode_reg.q[5]
mode_out[6] <= proc_mode_reg:I_proc_mode_reg.q[6]
mode_out[7] <= proc_mode_reg:I_proc_mode_reg.q[7]
sync_char1[0] <= proc_sync_reg:I_proc_sync_reg1.q[0]
sync_char1[1] <= proc_sync_reg:I_proc_sync_reg1.q[1]
sync_char1[2] <= proc_sync_reg:I_proc_sync_reg1.q[2]
sync_char1[3] <= proc_sync_reg:I_proc_sync_reg1.q[3]
sync_char1[4] <= proc_sync_reg:I_proc_sync_reg1.q[4]
sync_char1[5] <= proc_sync_reg:I_proc_sync_reg1.q[5]
sync_char1[6] <= proc_sync_reg:I_proc_sync_reg1.q[6]
sync_char1[7] <= proc_sync_reg:I_proc_sync_reg1.q[7]
sync_char2[0] <= proc_sync_reg:I_proc_sync_reg2.q[0]
sync_char2[1] <= proc_sync_reg:I_proc_sync_reg2.q[1]
sync_char2[2] <= proc_sync_reg:I_proc_sync_reg2.q[2]
sync_char2[3] <= proc_sync_reg:I_proc_sync_reg2.q[3]
sync_char2[4] <= proc_sync_reg:I_proc_sync_reg2.q[4]
sync_char2[5] <= proc_sync_reg:I_proc_sync_reg2.q[5]
sync_char2[6] <= proc_sync_reg:I_proc_sync_reg2.q[6]
sync_char2[7] <= proc_sync_reg:I_proc_sync_reg2.q[7]


|A8251|proc:i_procintf|proc_cmd_reg:I_proc_cmd_reg
mclk => int_proc_resetn1.CLK
mclk => cmd_reg[0].CLK
mclk => cmd_reg[1].CLK
mclk => cmd_reg[2].CLK
mclk => cmd_reg[3].CLK
mclk => cmd_reg[4].CLK
mclk => cmd_reg[5].CLK
mclk => cmd_reg[6].CLK
mclk => cmd_reg[7].CLK
rxclk => int_rx_resetn.CLK
rxclk => int_hunt2.CLK
rxclk => int_hunt1.CLK
txclk => int_tx_resetn.CLK
clr => int_hunt1.ACLR
clr => int_hunt2.ACLR
clr => rxsync_proc2~0.IN0
clr => int_proc_resetn1.ACLR
clr => cmd_reg[0].ACLR
clr => cmd_reg[1].ACLR
clr => cmd_reg[2].ACLR
clr => cmd_reg[3].ACLR
clr => cmd_reg[4].ACLR
clr => cmd_reg[5].ACLR
clr => cmd_reg[6].ACLR
clr => cmd_reg[7].ACLR
sclr => next_cmd_reg[7].OUTPUTSELECT
sclr => next_cmd_reg[6].OUTPUTSELECT
sclr => next_cmd_reg[5].OUTPUTSELECT
sclr => next_cmd_reg[4].OUTPUTSELECT
sclr => next_cmd_reg[3].OUTPUTSELECT
sclr => next_cmd_reg[2].OUTPUTSELECT
sclr => next_cmd_reg[1].OUTPUTSELECT
sclr => next_cmd_reg[0].OUTPUTSELECT
cmd_write => next_cmd_reg~0.OUTPUTSELECT
cmd_write => next_cmd_reg~1.OUTPUTSELECT
cmd_write => next_cmd_reg~2.OUTPUTSELECT
cmd_write => next_cmd_reg~3.OUTPUTSELECT
cmd_write => next_cmd_reg~4.OUTPUTSELECT
cmd_write => next_cmd_reg~5.OUTPUTSELECT
cmd_write => next_cmd_reg~6.OUTPUTSELECT
cmd_write => next_cmd_reg~7.OUTPUTSELECT
init => rxsync_proc2~0.IN1
din[0] => next_cmd_reg~7.DATAB
din[1] => next_cmd_reg~6.DATAB
din[2] => next_cmd_reg~5.DATAB
din[3] => next_cmd_reg~4.DATAB
din[4] => next_cmd_reg~3.DATAB
din[5] => next_cmd_reg~2.DATAB
din[6] => next_cmd_reg~1.DATAB
din[7] => next_cmd_reg~0.DATAB
hunt <= int_hunt~0.DB_MAX_OUTPUT_PORT_TYPE
error_resetn <= cmd_reg[4].DB_MAX_OUTPUT_PORT_TYPE
proc_resetn <= int_proc_resetn~0.DB_MAX_OUTPUT_PORT_TYPE
rx_resetn <= int_rx_resetn.DB_MAX_OUTPUT_PORT_TYPE
tx_resetn <= int_tx_resetn.DB_MAX_OUTPUT_PORT_TYPE
nRTS <= cmd_reg[5].DB_MAX_OUTPUT_PORT_TYPE
nDTR <= cmd_reg[1].DB_MAX_OUTPUT_PORT_TYPE
rx_enable <= cmd_reg[2].DB_MAX_OUTPUT_PORT_TYPE
tx_enable <= cmd_reg[0].DB_MAX_OUTPUT_PORT_TYPE
break_enable <= cmd_reg[3].DB_MAX_OUTPUT_PORT_TYPE


|A8251|proc:i_procintf|proc_mode_reg:I_proc_mode_reg
clk => int_dout[0].CLK
clk => int_dout[1].CLK
clk => int_dout[2].CLK
clk => int_dout[3].CLK
clk => int_dout[4].CLK
clk => int_dout[5].CLK
clk => int_dout[6].CLK
clk => int_dout[7].CLK
clr => int_dout[0].ACLR
clr => int_dout[1].ACLR
clr => int_dout[2].ACLR
clr => int_dout[3].ACLR
clr => int_dout[4].ACLR
clr => int_dout[5].ACLR
clr => int_dout[6].ACLR
clr => int_dout[7].ACLR
sclr => mux_dout[7].OUTPUTSELECT
sclr => mux_dout[6].OUTPUTSELECT
sclr => mux_dout[5].OUTPUTSELECT
sclr => mux_dout[4].OUTPUTSELECT
sclr => mux_dout[3].OUTPUTSELECT
sclr => mux_dout[2].OUTPUTSELECT
sclr => mux_dout[1].OUTPUTSELECT
sclr => mux_dout[0].OUTPUTSELECT
ce => mux_dout~0.OUTPUTSELECT
ce => mux_dout~1.OUTPUTSELECT
ce => mux_dout~2.OUTPUTSELECT
ce => mux_dout~3.OUTPUTSELECT
ce => mux_dout~4.OUTPUTSELECT
ce => mux_dout~5.OUTPUTSELECT
ce => mux_dout~6.OUTPUTSELECT
ce => mux_dout~7.OUTPUTSELECT
d[0] => mux_dout~7.DATAB
d[1] => mux_dout~6.DATAB
d[2] => mux_dout~5.DATAB
d[3] => mux_dout~4.DATAB
d[4] => mux_dout~3.DATAB
d[5] => mux_dout~2.DATAB
d[6] => mux_dout~1.DATAB
d[7] => mux_dout~0.DATAB
synch_mode <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
q[0] <= int_dout[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= int_dout[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= int_dout[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= int_dout[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= int_dout[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= int_dout[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= int_dout[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= int_dout[7].DB_MAX_OUTPUT_PORT_TYPE


|A8251|proc:i_procintf|proc_dec:I_proc_dec
reset => cmd_mode_write2.ACLR
reset => cmd_mode_write1.ACLR
reset => cmd_write2.ACLR
reset => cmd_write1.ACLR
ext_nWR => enable~0.IN0
ext_nWR => decode~1.IN0
nWR => decode~8.IN1
nRD => decode~3.IN1
nRD => decode~6.IN0
ext_CnD => enable~0.IN1
ext_CnD => decode~0.IN0
CnD => decode~5.IN1
CnD => decode~2.IN1
nCS => decode~4.IN1
nCS => decode~7.IN0
nCS => decode~9.IN0
clk => cmd_mode_write2.CLK
clk => cmd_mode_write1.CLK
clk => cmd_write2.CLK
clk => cmd_write1.CLK
init_done => decode~0.IN1
init_done => decode~2.IN0
init_done => decode~5.IN0
cmd_mode_write <= int_cmd_mode_write~0.DB_MAX_OUTPUT_PORT_TYPE
rx_read <= decode~4.DB_MAX_OUTPUT_PORT_TYPE
sts_read <= decode~7.DB_MAX_OUTPUT_PORT_TYPE
tx_fifo_wr_n <= decode~9.DB_MAX_OUTPUT_PORT_TYPE
cmd_write <= int_cmd_write~0.DB_MAX_OUTPUT_PORT_TYPE
cycle_rec <= cycle_rec~1.DB_MAX_OUTPUT_PORT_TYPE


|A8251|proc:i_procintf|proc_sm:I_proc_sm
scs => next_state~0.OUTPUTSELECT
scs => next_init_done~0.OUTPUTSELECT
wr_en => synch1_en~0.IN1
wr_en => synch2_en~0.IN1
wr_en => mode_en~0.IN1
wr_en => next_state~2.DATAB
wr_en => next_state~0.DATAB
wr_en => next_init_done~0.DATAA
wr_en => Selector0.IN4
wr_en => Selector2.IN2
wr_en => Selector1.IN2
wr_en => next_state~1.DATAB
reset => mode_gate.ACLR
reset => synch2_gate.ACLR
reset => synch1_gate.ACLR
reset => init_done~reg0.ACLR
reset => state~1.IN1
clr => next_state.mode.OUTPUTSELECT
clr => next_state.wait1.OUTPUTSELECT
clr => next_state.synch1.OUTPUTSELECT
clr => next_state.synch2.OUTPUTSELECT
clr => next_state.wait_reset.OUTPUTSELECT
clr => next_synch2_gate.OUTPUTSELECT
clr => next_synch1_gate.OUTPUTSELECT
clr => next_mode_gate.OUTPUTSELECT
clr => next_init_done.OUTPUTSELECT
clk => mode_gate.CLK
clk => synch2_gate.CLK
clk => synch1_gate.CLK
clk => init_done~reg0.CLK
clk => state~0.IN1
esd => states~0.IN0
synch => states~0.IN1
init_done <= init_done~reg0.DB_MAX_OUTPUT_PORT_TYPE
synch1_en <= synch1_en~0.DB_MAX_OUTPUT_PORT_TYPE
synch2_en <= synch2_en~0.DB_MAX_OUTPUT_PORT_TYPE
mode_en <= mode_en~0.DB_MAX_OUTPUT_PORT_TYPE