cdr14iic.c

IIC总线驱动程序

 *   while(DR04_IIC_IS_BUSY);
 *   // now all jobs are finished
 * }
 *
 * INTERFACE DECLARATION: ****************************************************/

void p_dr14_IICSchedule(u8 u8_Slave, const t_dr04_IICJob *pst_FirstJob)

{
  u32 x;

  /* get index to Control Block Queue and guard against overflow */
  SYS5_DISABLE_IRQ;

# ifndef BMP_TEST
  G_u8_os00_SystemActive = 1;
# endif
  
  if (st_dr14_IIC.u8_NumOfJobs >= DR14_MAX_JOBS)
  {
      /* insert behind current job */
      st_dr14_IIC.u8_NumOfJobs= 1;
      EXCEPTION(0xD2);
      /* transmissions (current+1, current+2) will be lost,
       * system will restart later */
  }

  /* now register job list */
  x= (st_dr14_IIC.u8_IdxActJob + st_dr14_IIC.u8_NumOfJobs) % DR14_MAX_JOBS;
  st_dr14_IIC.u8_NumOfJobs++;
  st_dr14_IIC.u8_Dev  [x]=   u8_Slave;
  st_dr14_IIC.pst_Jobs[x]=  pst_FirstJob;

  /* start IIC if necessary */
  if (st_dr14_IIC.u8_Busy == 0)
  {
      st_dr14_IIC.u8_Busy= 1;
      p_dr14_IICEndOfJob();
  }
  SYS5_ENABLE_IRQ;

} /* p_dr14_IICSchedule */


/* FUNCTIONAL DESCRIPTION
 *
 * This interrupt handler drives the transmission over the IIC bus.
 * Only the IIC Master Mode (Master Transmitter / Master Receiver)
 * is supported.
 *
 * INTERFACE DECLARATION: ****************************************************/


void p_dr14_IICInterrupt(void)
{

  /* DESIGN
   *
   * The state  of the interrupt source is fetched from the interrupt
   * state register S1STA and processed in a switch statement.
   */

  u32 u32_Rr;
  u8 u8_Wr=0;  /* if IIC_28_MT_DAT_ACK:       received ack on write       */
  u8 u8_Er=0;  /* if IIC_58_MR_DAT_NAK:       received last byte on read  */

# ifdef IIC_GPIO_TRACE
  /* GPIO_10 is pin 13 on the digital IO connector of the ABC PP */
  sys2_GPIO.PortPin[10].port_pin =1;
# endif
  
  u32_Rr= DR14_STATUS_REG;
  DR14_IIC_DUMP(DUMP_MARK,0xEE);
  DR14_IIC_DUMP(DUMP_STA,u32_Rr);

  switch (u32_Rr/*S1STA*/)
  {
    case DR14_IIC_10_MT_REPSTA_OK:         /* iic-bus started                */
    case DR14_IIC_08_MT_STA_OK:
      st_dr14_IIC.u8_StopRequested= 0;
      u32_Rr=   st_dr14_IIC.u8_Dev[st_dr14_IIC.u8_IdxActJob];
      u32_Rr |= st_dr14_IIC.st_ActTrf.un_Ctrl;
      DR14_DATA_REG= u32_Rr;
      /* SLA+W or SLA+R  */
      DR14_IIC_DUMP_CHECK(u32_Rr);
      DR14_IIC_DUMP(DUMP_DATW,u32_Rr);
      p_dr14_SetControl(DR14_IIC_FREE_ACK);
      break;

    case DR14_IIC_18_MT_SLA_ACK:           /* acknowledge on SLA+W           */
      DR14_DATA_REG= u32_Rr= *(u8 *)st_dr14_IIC.st_ActTrf.pu8_Buf;
      DR14_IIC_DUMP(DUMP_DATW,u32_Rr);
      p_dr14_SetControl(DR14_IIC_FREE_ACK);
      break;

    case DR14_IIC_58_MR_DAT_NAK:           /* last byte read                 */
      u8_Er= 1;
      /* no break; */
    case DR14_IIC_28_MT_DAT_ACK:           /* acknowledge on write byte      */
      u8_Wr= 1 - u8_Er;  /* ~u8_Er ist not the same for 8bit u8s! */
      /* no break */
    case DR14_IIC_50_MR_DAT_ACK:           /* data byte received (wr==0)     */
      /* store and count */
      if (!u8_Wr)
      {
          *(u8 *)st_dr14_IIC.st_ActTrf.pu8_Buf= u32_Rr= DR14_DATA_REG;
          DR14_IIC_DUMP(DUMP_DATR,u32_Rr);
      }
      st_dr14_IIC.st_ActTrf.pu8_Buf= (u8 *)st_dr14_IIC.st_ActTrf.pu8_Buf + 1;
      /* no break; */

    case DR14_IIC_40_MR_SLA_ACK:           /* acknowledge for SLA+R          */
      /*
      ** un_NBytes is already decremented in advance so
      ** it becomes zero before reception of the
      ** last byte
      */
      if(!u8_Er && --st_dr14_IIC.st_ActTrf.un_NBytes)
      {
          if (u8_Wr)
          {
              /* write next byte */
              DR14_DATA_REG = u32_Rr= *(u8 *)st_dr14_IIC.st_ActTrf.pu8_Buf;
              DR14_IIC_DUMP(DUMP_DATW,u32_Rr);
          }
          p_dr14_SetControl(DR14_IIC_FREE_ACK);    /* acknowledge for next */
      }
      else if (u8_Er|u8_Wr)
      {
          /* start nextJob or terminate ? */
          p_dr14_IICEndOfJob();
      }
      else
      {
          p_dr14_SetControl(DR14_IIC_FREE_NOACK);
          /* no ack to receive the last     */
      }
      break;


      /* handling errors
       * ****************************************************************/
    case DR14_IIC_38_MX_ARB_LOST:          /* lost arbitration             */
    case DR14_IIC_48_MR_SLA_NAK:           /* no acknowledge on SLA+R      */
    case DR14_IIC_20_MT_SLA_NAK:           /* no acknowledge on SLA+W      */
    case DR14_IIC_30_MT_DAT_NAK:           /* no acknowledge on write      */
    default: /* e.g.: 0x00, Bus Error caused by erroneous START or STOP */

#     ifdef IIC_GPIO_TRACE
      /* GPIO_11 is pin 14 on the digital IO connector of the ABC PP */
      sys2_GPIO.PortPin[11].port_pin =1;
      /* Allows to trigger the Oscilloscope when this pin is high for > 50us */
      delayUs(200);
      sys2_GPIO.PortPin[11].port_pin =0; 
      delayUs(10);
#     endif
      
      if (u32_Rr == DR14_IIC_38_MX_ARB_LOST)
      {
          DR14_IIC_DUMP(DUMP_MARK,0xE2);
          DR14_IIC_DUMP(DUMP_CON,DR14_CONTROL_REG);
          DR14_IIC_DUMP(DUMP_GPIODAT1,(u8)sys2_GPIO.dat1);
          p_dr14_SetControl(DR14_IIC_FREE_ACK);
      }
      else
      {
          DR14_IIC_DUMP(DUMP_MARK,0xE3);
          DR14_IIC_DUMP(DUMP_CON,DR14_CONTROL_REG);
          DR14_IIC_DUMP(DUMP_GPIODAT1,(u8)sys2_GPIO.dat1);
          p_dr14_SetControl(DR14_IIC_STOP);
      }
      DR14_IIC_CHECK_FREE;

      DR14_IIC_DUMP(DUMP_MARK,0xE4);
      DR14_IIC_DUMP(DUMP_CON,DR14_CONTROL_REG);
      DR14_IIC_DUMP(DUMP_GPIODAT1,(u8)sys2_GPIO.dat1);

#   if (DR14_IIC_ACK_REQUIRED!=2)
      if (st_dr14_IIC.u8_ErrorCount != 0) // retry (at first job of sequence)
      {
          st_dr14_IIC.u8_ErrorCount--;
          st_dr14_IIC.pst_Jobs[st_dr14_IIC.u8_IdxActJob]
            -= (st_dr14_IIC.u8_NextTrf - 1);
          st_dr14_IIC.u8_NextTrf= 0;
      }
#   endif      
#   if (DR14_IIC_ACK_REQUIRED==1)
      else
      {
          EXCEPTION(0xDD);
      }
#   endif
      st_dr14_IIC.u8_Abort= 1;
      st_dr14_IIC.u8_Sta= u32_Rr;
      p_dr14_IICEndOfJob();
      break; // error cases
  }
  
# ifdef IIC_GPIO_TRACE
  sys2_GPIO.PortPin[10].port_pin =0;
# endif
  
}  /* iic_interrupt */

/* FUNCTIONAL DESCRIPTION
 *
 * returns the state of the bus
 *
 *
 * PARAMETER
 * return         !=0      busy
 *                ==0      free
 *
 * INTERFACE DECLARATION: ****************************************************/

u32  p_dr14_IICBusy(void)
{
  return st_dr14_IIC.u8_Busy;
}


/* FUNCTIONAL DESCRIPTION:
 *
 * Returns the value of the DACKN signal which is provided by the IIC
 * converter card (IIC slave 0x90) to indicate that a data byte can be read.
 *
 * The value of DACKN is 'active low'.
 *
 * If the global flag G_u8_dr04_IICDacknDisable is set, the function will
 * always return 0. This might be useful if no DACKN line is available
 * and the software running in the converter card behaves gracefully
 * for read attempts when no data is present, i.e. it has to return
 * an escape character in that case.
 *
 * PARAMETER
 * return    1  DACKN signal is high => no data available
 *           0  DACKN signal is low  => data can be read
 *
 * INTERFACE DECLARATION: ****************************************************/

u32 p_dr14_IICDackn(void)
{
  u32 ret;
  if (st_dr14_IIC.u8_Dackn > SYS2_GPIO_MAX)
  {
      ret= 0; /* always 'Data ACKnowledge' */
  }
  else
  {
      ret= SYS2_GPIO_DAT_CHECK(st_dr14_IIC.u8_Dackn);
  }
  return ret;
} /* p_dr14_IICDackn */

/* FUNCTIONAL DESCRIPTION
 *
 * defines GPIO pin to be used as DACKN (does not GPIO properties DIR, UP, etc)
 *
 *
 * PARAMETER
 * u8_Pin         DACKN pin number, disables DACKN, if >SYS2_GPIO_MAX
 *
 * INTERFACE DECLARATION: ****************************************************/

void      p_dr14_IICSetDackn(u32 u8_Pin)
{
  st_dr14_IIC.u8_Dackn= u8_Pin;
  SYS2_GPIO_DIR_CLEAR(u8_Pin);
# ifdef VegaOne
  SYS2_GPIO_MUX_CLEAR(u8_Pin);
# endif  
}


/* FUNCTIONAL DESCRIPTION
 *
 * defines IIC clock
 *
 *
 * PARAMETER
 * u8_Clk         0/1/2/3 = 36, 48, 72, 96 kHz
 *
 * INTERFACE DECLARATION: ****************************************************/

void      p_dr14_IICSetClk(u32 u8_Clk)
{
  st_dr14_IIC.u8_Clk= u8_Clk;
}



/* FUNCTIONAL DESCRIPTION                                               
 *                                                                      
 * Initializes internal data of the IIC driver and starts the IIC hardware.
 *
 * INTERFACE DECLARATION: ****************************************************/

void p_dr14_IICInit()
{
# ifdef VegaOne /*-----------------------------------------------------*/
  {
      SYS2_GPIO_MUX_SET(SYS2_GPIO_IIC_SCL);
      SYS2_GPIO_DIR_SET(SYS2_GPIO_IIC_SCL);

      SYS2_GPIO_MUX_SET(SYS2_GPIO_IIC_SDA);
      SYS2_GPIO_DIR_SET(SYS2_GPIO_IIC_SDA);
  
      VOLAT_U32(sys0_SCU.pb_pcon_on) |= SYS0_SCU_IIC_POWER_MASK;
      VOLAT_U16(sys2_IIC.global) = SYS2_BLRES_IIC;
  }
  
# elif !defined(VegaPro) /*----------------------------------------------*/
  
  VOLATILE(sys2_GPIO.mux1,u16) |= SYS2_GPIO1_IIC_SEL;
# if defined(Pin64onDemoBlue) || defined(Pin80onDemoBlue)
  VOLATILE(sys2_GPIO.dir1,u16) |= (SYS2_GPIO1_01_IIC_SDA | SYS2_GPIO1_00_IIC_SCL);
  /* Enable IIC power supply on demoblue board*/
  sys2_GPIO.PortPin[23].port_pin = 0;
# elif defined(Pin180onCEPBB) || defined(PLATFORM_2)

  SYS2_GPIO_DIR_CLEAR(DR14_DACKN_GPIO);
  
# endif
  
  VOLAT_U32(sys0_SCU.pb_pcon_on) |= SYS0_SCU_IIC_POWER_MASK;
  VOLAT_U16(sys2_IIC.global) = SYS2_BLRES_IIC;
  
# else /* VegaPro --------------------------------------------------------*/
  sys2_GPIO.mux1 |= SYS2_GPIO1_IIC_SEL;
  
  VOLATILE(sys2_IIC.global, u16)= SYS2_BLRES_IIC | SYS2_IIC_ON;
  VOLATILE(sys2_IIC.global, u16)= SYS2_IIC_ON; /* this clears BLRES */
  VOLATILE(sys2_IIC.global, u16)= SYS2_IIC_ON; /* this turns IIC on */
# endif
  
  /* zeroing of global/static data already done by startup.a51
   * esp: st_dr14_IIC.u8_Clk= 0;  minimum frequency active by default
   */
  st_dr14_IIC.u8_StopRequested= 1;
  st_dr14_IIC.u8_ErrorCount=    DR14_IIC_MAX_ERRORS;
  p_dr14_IICSetDackn(DR14_DACKN_GPIO);

  /* S1ADR: address for slave modes | 1 if General Call is recognized */
  DR14_ADDRESS_REG = 0xE4;              /* SLA by IIC-bus commitee, no GC */
  
  p_dr14_SetControl(DR14_IIC_FREE_NOACK);

#ifdef PT_MODULE
  p_dr14_IICSetClk(SYS2_IIC_CLK48khz); /* LCDs are not fast enough for 96Hz */
#else
  p_dr14_IICSetClk(SYS2_IIC_CLK96khz);
#endif
  
  sys0_ICU.irq_enbs = SYS0_ICU_INT_IIC_IRQ;   /* enable IIC-interrupt */
} /* p_dr14_IICInit */