cdr14iic.c

IIC总线驱动程序

/* == IDENTIFICATION ==================================================
 *
 * Copyright (C) 2006, Philips Semiconductors Nuernberg
 *
 * System           : Vega Family
 * Component        : PT or FT
 * Module           : DRIVER
 * Unit             : IIC Bus Driver
 * File             : cdr14iic.c
 *
 *  @(#)   %filespec: cdr14iic.c-57 %
 *
 */

/* == HISTORY ========================================================= */
/*
 * Name      Date        Ver    Action
 * --------------------------------------------------------------------
 * tcmc_asb  10-Jan-2006  57  assert GPIO config when DACKN changes
 * tcmc_ore  22-Dec-2005  56  no DACKN if UART is used 
 * tcmc_hyu  13-Dec-2005  55  change DACKN to GPIO 10 for platform 2
 * tcmc_asb   5-Dec-2005  54  VegaOne, remove VOIP_HACK
 * tcmc_hyu  24-Jun-2005  52  remove warning: Undefined macro 'TBDemoboard'
 * tcmc_ore  23-Jun-2005  51  Merged version 50 and D75.2, init GPIO for IIC
 * tcmc_afn  02-Nov-2004 D75.2  Differnet DACKN pin in PT and FT for D75
 * tcmc_afn  19-Oct-2004 D75.1  Added pin DACKN = 31 for ANYLINE project
 * tcmc_ore  21-Feb-2005  50  Set default IIC Clock to 96KHz for VoIP
 * tcmc_afn  24-Aug-2004  49  Modified Pin80onDemoBlue when modem is present
 * tcmc_ore  30-Apr-2004 D68b.3 Added Pin80onDemoBlue
 * tcmc_ore  16-Apr-2004  47  Replace XSonDemoBlue with Pin64OnDemoBlue
 * tcmc_ore  23-Mar-2004  46  Add XSonDemoBlue switch
 * tcmc_asb  25-Feb-2004  45  D53, PR297: provide result control 
 *                            flexiblility for common use in diff. projects:
 *                                   p_dr14_IICSetDackn
 *                                   p_dr14_IICSetClk
 *                            Note: Version aligned to D51 archive
 * tcmc_ore  10-Dec-2002  21  PR157: Improve SET_CONTROL so that a requested
 *                                   STOP is checked, instead of the STATUS
 *                                   This resolves the problem that arises
 *                                   in SET_CONTROL(IIC_START) when the STOP
 *                                   was requested but the status was not yet
 *                                   reset to 0xF8 because the slave did
 *                                   CLOCK stretching.
 *                                   Together with Lothar we decided not to
 *                                   use this solution at 10-Dec-2002 because
 *                                   VT was happy with the version -20 (they
 *                                   received at 6-Dec-02), clock stretching is
 *                                   only done by very old devices, and no
 *                                   one has time to test this right now!
 *                                   Nevertheless this new driver here did
 *                                   also not show any errors in TBR10 with
 *                                   additional IIC activity.
 *        
 * tcmc_ore   6-Dec-2002  20  PR157: Add some comments
 * tcmc_ore   4-Dec-2002  19  PR157: Change SET_CONTROL and add more
 *                                   debug info (#ifdef IIC_DUMP_SIZE)
 *                                   add IIC_GPIO_TRACE
 * tcmc_dbm  27-Nov-2002      add Switch for VegaLite
 * tcmc_hyu  22-Apr-2002      changes for VegaXS
 * tcmc_hyu  18-Apr-2002      delete Pullup setting for Dackn. This is
                              done in cdr10int.c
 * tcmc_hyu  18-Apr-2002      use GPIO 24 as Dackn for VegaTB demoboard
 * tcmc_ore  26-Mar-2002      use IIC Clock of 36kHz for VegaTB too (LCD)
 * tcmc_hyu  26-Feb-2002      correct DR14_SET_CONTROL as suggested by asb
 * tcmc_hyu  07-Feb-2002      changes for VegaTB
 * tcmc_ore  23-Jan-2002      no SystemActive flag for BMP_TEST
 * tcmc_hyu  22-Jan-2002      first attempt to make it compile for VegaTB
 * tcmc_ore  11-Dec-2001      set SystemActive flag in IICSchedule
 * tcmc_hyu  19-Nov-2001      add semi-colon in empty while loop
 * tcmc_hyu  15-Nov-2001      correct use of curly braces
 * tcmc_hyu  07-Nov-2001      rework after code crosscheck
 * tcmc_asa  19-Oct-2001      change t_iic_exec to t_dr04_IICExecute
 * tcmc_asa  08-Aug-2001      SYS2_GPIO1_13_UART_RTS used for DACKN
 * tcmc_asa  17-Jul-2001      remove bbc.h 
 * tcmc_hyu  31-May-2001      SYS2_GPIO2_29_CS_N2 used for DACKN
 *                            signal instead of SYS2_GPIO2_21_KBIO6
 * tcmc_asa  30-Nov-2000      created, copied from D46 dr_iic.c
 *                                             
 */


/*MPM:::DRIVER::IIC Bus===================================================
 *
 * ABSTRACT:
 *
 * This module comprises routines to access any device connected
 * to the IIC bus. The driver operates in master mode only.
 * The function list also includes some macros defined in cdr04iic.h.
 *
 * Global functions to be called by other layers:
 * ----------------------------------------------
 * - p_dr14_IICDackn
 * - p_dr14_IICImmediate 
 * - p_dr14_IICRead  
 * - p_dr14_IICSchedule  
 * - p_dr14_IICTransmit  
 * - p_dr14_IICWrite 
 *
 * Layer local functions to be called from inside this layer:
 * ----------------------------------------------------------
 * - p_dr14_IICInit
 * - p_dr14_IICSetDackn
 * - p_dr14_IICSetClk
 *
 * Module-local functions to be called from inside this module:
 * ------------------------------------------------------------
 * - p_dr14_IICEndOfJob  
 * - p_dr14_IICInterrupt
 */


/* == DESIGN ==========================================================
 *
 * The driver operates on a queue of t_dr04_IICJob, each of them consisting
 * of an arbitrary number of transmission steps.
 *
 * The function p_dr14_IICSchedule accepts an t_dr04_IICJob, puts it into the
 * queue and activates the IIC bus if necessary. It returns to the
 * caller asynchronously, without waiting for completion.
 *
 * According to the signals on the IIC bus the driver is invoked at
 * p_dr14_IICInterrupt and communicates with the IIC controller according
 * to the state of the IIC bus and the transmission in progress.
 * The p_dr14_IICInterrupt function will continue transmissions on the bus
 * until the queue becomes empty.
 *
 * The remaining interface functions are build around the asynchronous
 * driver kernel formed by p_dr14_IICSchedule and p_dr14_IICInterrupt.
 *
 */


/* == GLOBAL DECLARATIONS            ======================================= */

#define cdr14_c

#include <string.h>           /* memmove */
#include "cg0type.h"
#ifndef BMP_TEST
#include "cos00int.h"
#endif
#include "tclib.h"

#include "cdr04iic.h"
#include "csys5os.h"
#include "csys0reg.h"
#include "csys2vpb.h"

#ifndef             SYS2_GPIO_MAX
# ifndef VegaPro
#  define           SYS2_GPIO_MAX 34
# else
#  define           SYS2_GPIO_MAX 31
# endif
#endif

#ifndef   EXCEPTION
void      p_dr14_IICException(u32 u32_X)
{
  while(1);
}
# define  EXCEPTION(x) p_dr14_IICException(x)
#endif
/* == DECLARATION OF MODULE LOCAL DATA ================================ */

/* S1STA codes
 * *************/
#define DR14_CONTROL_REG    (sys2_IIC.con)
#define DR14_STATUS_REG     (sys2_IIC.sta)
#define DR14_DATA_REG       (sys2_IIC.dat)
#define DR14_ADDRESS_REG    (sys2_IIC.adr)

#define DR14_IIC_00_BUS_ERROR        0x00  /* erroneous START/STOP on bus    */

/* Master Transmitter mode      S1STA values */
#define DR14_IIC_08_MT_STA_OK        0x08  /* STArt condition generated      */
#define DR14_IIC_10_MT_REPSTA_OK     0x10  /* REPeatedSTA (w/o STOP)         */
#define DR14_IIC_18_MT_SLA_ACK       0x18  /* SLA+W sent, ACK rcvd           */
#define DR14_IIC_20_MT_SLA_NAK       0x20  /* SLA+W sent, NAK rcvd           */
#define DR14_IIC_28_MT_DAT_ACK       0x28  /* DAT sent, ACK rcvd             */
#define DR14_IIC_30_MT_DAT_NAK       0x30  /* DAT sent, NAK rcvd             */

/* Master looses arbitration, but is not addressed as slave */
#define DR14_IIC_38_MX_ARB_LOST      0x38  /* current Read/Write aborted     */

/* Master Receiver mode         S1STA values */
#define DR14_IIC_40_MR_SLA_ACK       0x40  /* SLA+R sent, ACK rcvd           */
#define DR14_IIC_48_MR_SLA_NAK       0x48  /* SLA+R sent, NAK rcvd           */
#define DR14_IIC_50_MR_DAT_ACK       0x50  /* DAT rcvd, ACK rcvd             */
#define DR14_IIC_58_MR_DAT_NAK       0x58  /* DAT rcvd, NAK rcvd             */

/* Slave Receiver mode          S1STA values */
#define DR14_IIC_60_SR_SLA_ACK       0x60  /* own SLA+W rcvd, ACK sent       */
#define DR14_IIC_68_SR_SLA_ACK_ARB   0x68  /* arb.lost, SLA+W rcvd, ACK sent */
#define DR14_IIC_70_SR_GC_ACK        0x70  /* GC (0x00=GC+W)  rcvd, ACK sent */
#define DR14_IIC_78_SR_GC_ACK_ARB    0x78  /* arb.lost, GC rcvd, ACK sent    */
#define DR14_IIC_80_SR_DAT_ACK       0x80  /* DAT rcvd, ACK sent             */
#define DR14_IIC_88_SR_DAT_NAK       0x88  /* DAT rcvd, NAK sent             */
#define DR14_IIC_90_SR_GC_DAT_ACK    0x90  /* DAT rcvd, ACK sent, in GC      */
#define DR14_IIC_98_SR_GC_DAT_NAK    0x98  /* DAT rcvd, NAK sent, in GC      */

/* Slave rcv STOP condition     S1STA value */
#define DR14_IIC_A0_SX_STP           0xA0  /* SToP or REPeated STArt rcvd    */

/* Slave Transmitter mode       S1STA values */
#define DR14_IIC_A8_ST_SLA_ACK       0xA8  /* own SLA+R rcvd, ACK sent       */
#define DR14_IIC_B0_ST_SLA_ACK_ARB   0xB0  /* arb.lost, SLA+R rcvd, ACK sent */
#define DR14_IIC_B8_ST_DAT_ACK       0xB8  /* DAT sent, ACK rcvd             */
#define DR14_IIC_C0_ST_DAT_NAK       0xC0  /* DAT sent, NAK rcvd             */
#define DR14_IIC_C8_ST_DATNAK_ACK    0xC8  /* DAT+NAK sent, ACK rcvd         */

/* IIC controller is busy */
#define DR14_IIC_F8_SIO_BUSY         0xF8  /* SIO hw busy, SI bit is 0       */


/* Data ackowledge pin definition */
#ifdef TWO_LINE_BOARD
# if defined (PT_MODULE)
#define DR14_DACKN_GPIO               13
# else
#define DR14_DACKN_GPIO               31
# endif
#elif defined(TBDemoboard)
#define DR14_DACKN_GPIO               24
#elif defined(Pin180onCEPBB)
#define DR14_DACKN_GPIO                7
#elif defined(PLATFORM_2)
#ifdef UART
#define DR14_DACKN_GPIO               0xFF /* no DACKN, GPIO 10 is RXD on 100pin VegaBB */
#else
#define DR14_DACKN_GPIO               10
#endif
#elif defined(Pin64onDemoBlue)
#define DR14_DACKN_GPIO               21
#elif defined(Pin80onDemoBlue)
#if (DA_MAX_MODEM > 0)
#define DR14_DACKN_GPIO               21
#else
#define DR14_DACKN_GPIO               13
#endif /* DA_MAX_MODEM>0 */
#else
#if (DA_MAX_MODEM > 0)
#define DR14_DACKN_GPIO               21
#else
#define DR14_DACKN_GPIO               13
#endif /* DA_MAX_MODEM>0 */
#endif

/* S1CON bits
 * ************/
#define DR14_IIC_CLK  (st_dr14_IIC.u8_Clk)
#define DR14_IIC_ENA  0x40
#define DR14_IIC_STA  0x20
#define DR14_IIC_STP  0x10
#define DR14_IIC_AA   0x04


#define DUMP_CON      'C'
#define DUMP_DATR     'R'
#define DUMP_DATW     'W'
#define DUMP_STA      'S'
#define DUMP_MARK     'M'
#define DUMP_GPIODAT1 'G'


#define DR14_IIC_DISABLE    (DR14_IIC_CLK                                 )
#define DR14_IIC_START      (DR14_IIC_CLK | DR14_IIC_ENA  | DR14_IIC_STA  )
#define DR14_IIC_STOP       (DR14_IIC_CLK | DR14_IIC_ENA  | DR14_IIC_STP  )
#define DR14_IIC_FREE_ACK   (DR14_IIC_CLK | DR14_IIC_ENA  | DR14_IIC_AA   )
#define DR14_IIC_FREE_NOACK (DR14_IIC_CLK | DR14_IIC_ENA                  )


void p_dr14_SetControl(u32 conVal);

/* debugging aid
 * **************/
#ifndef   IIC_DUMP_SIZE
#  define IIC_DUMP_SIZE     0
#endif
#define DR14_IIC_DUMP_SLAVE    0x90

#if IIC_DUMP_SIZE>0
u16    u16_IICDumpX;
u8      u8_IICDumpFlag;
u8      u8_IICDump[IIC_DUMP_SIZE][2];
# define DR14_IIC_DUMP(what,byt)                                  \
              if(u8_IICDumpFlag)                                  \
              {                                                   \
                  u8_IICDump[u16_IICDumpX][0]=(u8)(what);         \
                  u8_IICDump[u16_IICDumpX][1]=(u8)(byt);          \
                  u16_IICDumpX= (u16_IICDumpX+1)%IIC_DUMP_SIZE;   \
              }
# define DR14_IIC_DUMP_CHECK(rr)                                  \
      if ((rr)==DR14_IIC_DUMP_SLAVE) /* check for slave to be dumped */  \
      {                                                           \
          u8_IICDumpFlag= 1;                                      \
      }
# define DR14_IIC_DUMP_STOP  u8_IICDumpFlag= 1  /* never stops */

# if 0
#  define DR14_IIC_CHECK_FREE p_dr14_IICCheckFree()
# else
#  define DR14_IIC_CHECK_FREE 
# endif

/* FUNCTIONAL DESCRIPTION
 *
 * Debug function to check if the IIC bus is free.
 *
 * PARAMETER
 * none
 *
 * INTERFACE DECLARATION: ****************************************************/
void p_dr14_IICCheckFree(void)
{
  u32 u32_Cnt;

  for (u32_Cnt=0; (VOLATILE(sys2_GPIO.dat1,u16)&3)!=3; u32_Cnt++)
  {
      DR14_IIC_DUMP(DUMP_CON,DR14_CONTROL_REG);
      DR14_IIC_DUMP(DUMP_STA,DR14_STATUS_REG);
      while (u32_Cnt>1400) /* divided by 7 gives min.number of micro seconds */
      {
          /* break here to check hardware */
          p_dr14_SetControl(DR14_IIC_STOP);
      }
  }
} /* p_dr14_IICCheckFree */


#else /* IIC_DUMP_SIZE==0  i.e. no debugging code */


# define DR14_IIC_DUMP(what,byt)
# define DR14_IIC_DUMP_CHECK(rr)
# define DR14_IIC_DUMP_STOP
# define DR14_IIC_CHECK_FREE
#endif /* IIC_DUMP_SIZE */

/*
** IIC_ACK_REQUIRED controls default reaction on NOACK error conditions per
**                  conditional compilation
**   1 => treat NOACK as error after retries, i.e. devices must be ready,
**        otherwise an exception is raised
**   2 => terminate transmission on NOACK, i.e. device allowed tempoarily
**        offline, but no retries (clients may use DR04_IIC_RESULT)
**   3 => perform retries on NOACK, ignore job if retries fail
*/
#define DR14_IIC_ACK_REQUIRED 2
#define DR14_IIC_MAX_ERRORS   5 /* in case of DR14_IIC_ACK_REQUIRED!=2 */


/*
 * STATIC DATA
 * ***********
 */

#define     DR14_MAX_JOBS            8