print1.vhd

来自「用VHDL编写的简单POC（并行输出控制）程序」· VHDL 代码 · 共 30 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY PRINT1 IS
	PORT (RDY:BUFFER STD_LOGIC; TR, CLK, RESET: IN STD_LOGIC);
END PRINT1;

ARCHITECTURE BEHAVIOR OF PRINT1 IS
	SIGNAL COUNT: INTEGER RANGE 0 TO 3;
BEGIN
	PROCESS(CLK, TR)
	BEGIN
	IF RESET = '1' THEN
		RDY <= '1';
	ELSIF TR='1' THEN
		RDY <= '0';
		COUNT <= 0;
	ELSIF RISING_EDGE(CLK) THEN
		IF RDY = '0' THEN
			IF COUNT = 3 THEN
				RDY <= '1';
			END IF;
			COUNT <= COUNT + 1;
		END IF;
	END IF;
	END PROCESS;
END BEHAVIOR;