📄 systerm.rpt
字号:
- 8 - A 20 DFFE + 1 2 0 4 |POC3:1|CURRENT_STATE1 (|POC3:1|:27)
- 3 - A 20 DFFE + ! 0 3 0 3 |POC3:1|CURRENT_STATE0 (|POC3:1|:28)
- 7 - C 16 DFFE + 1 2 0 1 |POC3:1|SR6 (|POC3:1|:32)
- 8 - C 22 DFFE + 1 2 0 1 |POC3:1|SR5 (|POC3:1|:33)
- 4 - C 22 DFFE + 1 2 0 1 |POC3:1|SR4 (|POC3:1|:34)
- 8 - B 17 DFFE + 1 2 0 1 |POC3:1|SR3 (|POC3:1|:35)
- 4 - B 17 DFFE + 1 2 0 1 |POC3:1|SR2 (|POC3:1|:36)
- 6 - A 13 DFFE + 1 2 0 1 |POC3:1|SR1 (|POC3:1|:37)
- 7 - A 20 DFFE + 1 2 0 2 |POC3:1|SR0 (|POC3:1|:38)
- 7 - C 23 DFFE + 0 2 1 1 |POC3:1|BR7 (|POC3:1|:39)
- 6 - C 16 DFFE + 0 2 1 1 |POC3:1|BR6 (|POC3:1|:40)
- 6 - C 22 DFFE + 0 2 1 1 |POC3:1|BR5 (|POC3:1|:41)
- 1 - C 22 DFFE + 0 2 1 1 |POC3:1|BR4 (|POC3:1|:42)
- 5 - B 17 DFFE + 0 2 1 1 |POC3:1|BR3 (|POC3:1|:43)
- 3 - B 17 DFFE + 0 2 1 1 |POC3:1|BR2 (|POC3:1|:44)
- 4 - A 13 DFFE + 0 2 1 1 |POC3:1|BR1 (|POC3:1|:45)
- 8 - A 13 DFFE + 0 2 1 1 |POC3:1|BR0 (|POC3:1|:46)
- 7 - A 13 OR2 s 1 2 0 8 |POC3:1|~326~1
- 2 - C 16 AND2 s 4 0 0 17 |POC3:1|~530~1
- 1 - C 16 OR2 1 3 1 0 |POC3:1|:644
- 8 - C 16 AND2 1 2 0 1 |POC3:1|:646
- 1 - A 13 OR2 ! 1 2 0 0 |POC3:1|:658
- 3 - C 16 OR2 1 3 1 0 |POC3:1|:659
- 5 - C 16 AND2 1 2 0 1 |POC3:1|:661
- 5 - C 22 OR2 1 3 1 0 |POC3:1|:674
- 7 - C 22 AND2 1 2 0 1 |POC3:1|:676
- 2 - C 22 OR2 1 3 1 0 |POC3:1|:689
- 3 - C 22 AND2 1 2 0 1 |POC3:1|:691
- 1 - B 17 OR2 1 3 1 0 |POC3:1|:704
- 6 - B 17 AND2 1 2 0 1 |POC3:1|:706
- 7 - B 17 OR2 1 3 1 0 |POC3:1|:719
- 2 - B 17 AND2 1 2 0 1 |POC3:1|:721
- 3 - A 13 OR2 1 3 1 0 |POC3:1|:734
- 2 - A 13 AND2 1 2 0 1 |POC3:1|:736
- 5 - A 13 OR2 1 3 1 0 |POC3:1|:749
- 1 - A 20 AND2 1 2 0 1 |POC3:1|:750
- 4 - C 16 AND2 s 4 0 0 12 |POC3:1|~1043~1
- 2 - A 20 AND2 1 1 0 1 |POC3:1|:1043
- 4 - A 20 AND2 0 2 0 1 |POC3:1|:1127
- 6 - A 20 AND2 ! 0 1 1 3 |POC3:1|:1257
- 5 - A 20 OR2 ! 0 3 1 0 |POC3:1|:1305
- 1 - A 16 DFFE + 0 3 1 3 |PRINT:12|:1
- 4 - A 16 DFFE + 0 4 0 1 |PRINT:12|COUNT1 (|PRINT:12|:6)
- 3 - A 16 DFFE + 0 3 0 2 |PRINT:12|COUNT0 (|PRINT:12|:7)
- 2 - A 16 SOFT s ! 1 0 0 2 RESET~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: d:\yuhui\systerm.rpt
systerm
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 0/ 48( 0%) 9/ 48( 18%) 0/16( 0%) 4/16( 25%) 1/16( 6%)
B: 5/ 96( 5%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 2/16( 12%) 2/16( 12%)
C: 9/ 96( 9%) 0/ 48( 0%) 7/ 48( 14%) 1/16( 6%) 3/16( 18%) 4/16( 25%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 0/4( 0%) 1/4( 25%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: d:\yuhui\systerm.rpt
systerm
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 20 CLK
Device-Specific Information: d:\yuhui\systerm.rpt
systerm
** CLEAR SIGNALS **
Type Fan-out Name
LCELL 4 |POC3:1|:1257
INPUT 4 RESET
Device-Specific Information: d:\yuhui\systerm.rpt
systerm
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
CLK : INPUT;
CS : INPUT;
RESET : INPUT;
RW : INPUT;
-- Node name is 'D0'
-- Equation name is 'D0', type is bidir
D0 = TRI(_LC5_A13, !_LC1_A13);
-- Node name is 'D1'
-- Equation name is 'D1', type is bidir
D1 = TRI(_LC3_A13, !_LC1_A13);
-- Node name is 'D2'
-- Equation name is 'D2', type is bidir
D2 = TRI(_LC7_B17, !_LC1_A13);
-- Node name is 'D3'
-- Equation name is 'D3', type is bidir
D3 = TRI(_LC1_B17, !_LC1_A13);
-- Node name is 'D4'
-- Equation name is 'D4', type is bidir
D4 = TRI(_LC2_C22, !_LC1_A13);
-- Node name is 'D5'
-- Equation name is 'D5', type is bidir
D5 = TRI(_LC5_C22, !_LC1_A13);
-- Node name is 'D6'
-- Equation name is 'D6', type is bidir
D6 = TRI(_LC3_C16, !_LC1_A13);
-- Node name is 'D7'
-- Equation name is 'D7', type is bidir
D7 = TRI(_LC1_C16, !_LC1_A13);
-- Node name is 'IRQ'
-- Equation name is 'IRQ', type is output
IRQ = !_LC5_A20;
-- Node name is 'PD0'
-- Equation name is 'PD0', type is output
PD0 = TRI(_LC8_A13, !_LC4_A20);
-- Node name is 'PD1'
-- Equation name is 'PD1', type is output
PD1 = TRI(_LC4_A13, !_LC4_A20);
-- Node name is 'PD2'
-- Equation name is 'PD2', type is output
PD2 = TRI(_LC3_B17, !_LC4_A20);
-- Node name is 'PD3'
-- Equation name is 'PD3', type is output
PD3 = TRI(_LC5_B17, !_LC4_A20);
-- Node name is 'PD4'
-- Equation name is 'PD4', type is output
PD4 = TRI(_LC1_C22, !_LC4_A20);
-- Node name is 'PD5'
-- Equation name is 'PD5', type is output
PD5 = TRI(_LC6_C22, !_LC4_A20);
-- Node name is 'PD6'
-- Equation name is 'PD6', type is output
PD6 = TRI(_LC6_C16, !_LC4_A20);
-- Node name is 'PD7'
-- Equation name is 'PD7', type is output
PD7 = TRI(_LC7_C23, !_LC4_A20);
-- Node name is 'RDY'
-- Equation name is 'RDY', type is output
RDY = _LC1_A16;
-- Node name is 'RESET~1'
-- Equation name is 'RESET~1', location is LC2_A16, type is buried.
-- synthesized logic cell
!_LC2_A16 = _LC2_A16~NOT;
_LC2_A16~NOT = LCELL(!RESET);
-- Node name is 'TR'
-- Equation name is 'TR', type is output
TR = _LC6_A20;
-- Node name is '|POC3:1|:46' = '|POC3:1|BR0'
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = DFFE( _EQ001, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ001 = D0 & !_LC7_A13
# _LC7_A13 & _LC8_A13;
-- Node name is '|POC3:1|:45' = '|POC3:1|BR1'
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = DFFE( _EQ002, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ002 = D1 & !_LC7_A13
# _LC4_A13 & _LC7_A13;
-- Node name is '|POC3:1|:44' = '|POC3:1|BR2'
-- Equation name is '_LC3_B17', type is buried
_LC3_B17 = DFFE( _EQ003, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ003 = D2 & !_LC7_A13
# _LC3_B17 & _LC7_A13;
-- Node name is '|POC3:1|:43' = '|POC3:1|BR3'
-- Equation name is '_LC5_B17', type is buried
_LC5_B17 = DFFE( _EQ004, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ004 = D3 & !_LC7_A13
# _LC5_B17 & _LC7_A13;
-- Node name is '|POC3:1|:42' = '|POC3:1|BR4'
-- Equation name is '_LC1_C22', type is buried
_LC1_C22 = DFFE( _EQ005, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ005 = D4 & !_LC7_A13
# _LC1_C22 & _LC7_A13;
-- Node name is '|POC3:1|:41' = '|POC3:1|BR5'
-- Equation name is '_LC6_C22', type is buried
_LC6_C22 = DFFE( _EQ006, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ006 = D5 & !_LC7_A13
# _LC6_C22 & _LC7_A13;
-- Node name is '|POC3:1|:40' = '|POC3:1|BR6'
-- Equation name is '_LC6_C16', type is buried
_LC6_C16 = DFFE( _EQ007, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ007 = D6 & !_LC7_A13
# _LC6_C16 & _LC7_A13;
-- Node name is '|POC3:1|:39' = '|POC3:1|BR7'
-- Equation name is '_LC7_C23', type is buried
_LC7_C23 = DFFE( _EQ008, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ008 = D7 & !_LC7_A13
# _LC7_A13 & _LC7_C23;
-- Node name is '|POC3:1|:28' = '|POC3:1|CURRENT_STATE0'
-- Equation name is '_LC3_A20', type is buried
!_LC3_A20 = _LC3_A20~NOT;
_LC3_A20~NOT = DFFE( _EQ009, GLOBAL(!CLK), GLOBAL(!RESET), VCC, VCC);
_EQ009 = _LC8_A20
# !_LC1_A16 & !_LC3_A20
# !_LC1_A16 & _LC2_A20
# _LC2_A20 & _LC3_A20;
-- Node name is '|POC3:1|:27' = '|POC3:1|CURRENT_STATE1'
-- Equation name is '_LC8_A20', type is buried
_LC8_A20 = DFFE( _EQ010, GLOBAL(!CLK), GLOBAL(!RESET), VCC, VCC);
_EQ010 = _LC3_A20 & _LC4_C16 & !_LC8_A20 & RW;
-- Node name is '|POC3:1|:38' = '|POC3:1|SR0'
-- Equation name is '_LC7_A20', type is buried
_LC7_A20 = DFFE( _EQ011, GLOBAL(!CLK), VCC, VCC, VCC);
_EQ011 = D0 & _LC2_C16 & RW
# _LC7_A20 & !RW
# !_LC2_C16 & _LC7_A20;
-- Node name is '|POC3:1|:37' = '|POC3:1|SR1'
-- Equation name is '_LC6_A13', type is buried
_LC6_A13 = DFFE( _EQ012, GLOBAL(!CLK), VCC, VCC, VCC);
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -