📄 at91sam9260.inc
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;- ----------------------------------------------------------------------------
;- ATMEL Microcontroller Software Support - ROUSSET -
;- ----------------------------------------------------------------------------
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;- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;- ----------------------------------------------------------------------------
;- File Name : AT91SAM9260.h
;- Object : AT91SAM9260 definitions
;- Generated : AT91 SW Application Group 09/30/2005 (14:09:33)
;-
;- CVS Reference : /AT91SAM9260.pl/1.8/Fri Sep 30 08:12:29 2005//
;- CVS Reference : /SYS_SAM9260.pl/1.1/Mon Jul 04 09:07:10 2005//
;- CVS Reference : /HMATRIX1_SAM9260.pl/0/dummy timestamp//
;- CVS Reference : /CCR_SAM9260.pl/0/dummy timestamp//
;- CVS Reference : /PMC_SAM9260.pl/0/dummy timestamp//
;- CVS Reference : /ADC_6051C.pl/1.1/Mon Jan 31 13:12:40 2005//
;- CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 09 10:52:25 2004//
;- CVS Reference : /HSMC3_6105A.pl/1.4/Tue Nov 16 09:16:23 2004//
;- CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
;- CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 03 09:02:11 2005//
;- CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
;- CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 03 10:29:42 2005//
;- CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 04 13:57:00 2004//
;- CVS Reference : /SHDWC_6122A.pl/1.3/Wed Oct 06 14:16:58 2004//
;- CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 04 13:57:22 2004//
;- CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 04 13:56:22 2004//
;- CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 04 13:58:52 2004//
;- CVS Reference : /TC_6082A.pl/1.7/Wed Mar 09 16:31:51 2005//
;- CVS Reference : /MCI_6101E.pl/1.1/Fri Jun 03 13:20:23 2005//
;- CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 06:38:23 2004//
;- CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
;- CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:10:41 2004//
;- CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
;- CVS Reference : /EMACB_6119A.pl/1.6/Wed Jul 13 15:25:00 2005//
;- CVS Reference : /UDP_6083C.pl/1.2/Tue May 10 12:40:17 2005//
;- CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
;- CVS Reference : /TBOX_XXXX.pl/1.15/Thu Jun 09 07:05:57 2005//
;- CVS Reference : /EBI_SAM9260.pl/0/dummy timestamp//
;- CVS Reference : /HECC_6143A.pl/1.1/Wed Feb 09 17:16:57 2005//
;- CVS Reference : /ISI_xxxxx.pl/1.3/Thu Mar 03 11:11:48 2005//
;- ----------------------------------------------------------------------------
;- Hardware register definition
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR System Peripherals
;- *****************************************************************************
;- -------- GPBR : (SYS Offset: 0x1350) GPBR General Purpose Register --------
;- -------- GPBR : (SYS Offset: 0x1354) GPBR General Purpose Register --------
;- -------- GPBR : (SYS Offset: 0x1358) GPBR General Purpose Register --------
;- -------- GPBR : (SYS Offset: 0x135c) GPBR General Purpose Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR External Bus Interface
;- *****************************************************************************
^ 0 ;- AT91S_EBI
EBI_DUMMY # 4 ;- Dummy register - Do not use
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Error Correction Code controller
;- *****************************************************************************
^ 0 ;- AT91S_ECC
ECC_CR # 4 ;- ECC reset register
ECC_MR # 4 ;- ECC Page size register
ECC_SR # 4 ;- ECC Status register
ECC_PR # 4 ;- ECC Parity register
ECC_NPR # 4 ;- ECC Parity N register
# 232 ;- Reserved
ECC_VR # 4 ;- ECC Version register
;- -------- ECC_CR : (ECC Offset: 0x0) ECC reset register --------
AT91C_ECC_RST EQU (0x1:SHL:0) ;- (ECC) ECC reset parity
;- -------- ECC_MR : (ECC Offset: 0x4) ECC page size register --------
AT91C_ECC_PAGE_SIZE EQU (0x3:SHL:0) ;- (ECC) Nand Flash page size
;- -------- ECC_SR : (ECC Offset: 0x8) ECC status register --------
AT91C_ECC_RECERR EQU (0x1:SHL:0) ;- (ECC) ECC error
AT91C_ECC_ECCERR EQU (0x1:SHL:1) ;- (ECC) ECC single error
AT91C_ECC_MULERR EQU (0x1:SHL:2) ;- (ECC) ECC_MULERR
;- -------- ECC_PR : (ECC Offset: 0xc) ECC parity register --------
AT91C_ECC_BITADDR EQU (0xF:SHL:0) ;- (ECC) Bit address error
AT91C_ECC_WORDADDR EQU (0xFFF:SHL:4) ;- (ECC) address of the failing bit
;- -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register --------
AT91C_ECC_NPARITY EQU (0xFFFF:SHL:0) ;- (ECC) ECC parity N
;- -------- ECC_VR : (ECC Offset: 0xfc) ECC version register --------
AT91C_ECC_VR EQU (0xF:SHL:0) ;- (ECC) ECC version register
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR SDRAM Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_SDRAMC
SDRAMC_MR # 4 ;- SDRAM Controller Mode Register
SDRAMC_TR # 4 ;- SDRAM Controller Refresh Timer Register
SDRAMC_CR # 4 ;- SDRAM Controller Configuration Register
SDRAMC_HSR # 4 ;- SDRAM Controller High Speed Register
SDRAMC_LPR # 4 ;- SDRAM Controller Low Power Register
SDRAMC_IER # 4 ;- SDRAM Controller Interrupt Enable Register
SDRAMC_IDR # 4 ;- SDRAM Controller Interrupt Disable Register
SDRAMC_IMR # 4 ;- SDRAM Controller Interrupt Mask Register
SDRAMC_ISR # 4 ;- SDRAM Controller Interrupt Mask Register
SDRAMC_MDR # 4 ;- SDRAM Memory Device Register
;- -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
AT91C_SDRAMC_MODE EQU (0xF:SHL:0) ;- (SDRAMC) Mode
AT91C_SDRAMC_MODE_NORMAL_CMD EQU (0x0) ;- (SDRAMC) Normal Mode
AT91C_SDRAMC_MODE_NOP_CMD EQU (0x1) ;- (SDRAMC) Issue a NOP Command at every access
AT91C_SDRAMC_MODE_PRCGALL_CMD EQU (0x2) ;- (SDRAMC) Issue a All Banks Precharge Command at every access
AT91C_SDRAMC_MODE_LMR_CMD EQU (0x3) ;- (SDRAMC) Issue a Load Mode Register at every access
AT91C_SDRAMC_MODE_RFSH_CMD EQU (0x4) ;- (SDRAMC) Issue a Refresh
AT91C_SDRAMC_MODE_EXT_LMR_CMD EQU (0x5) ;- (SDRAMC) Issue an Extended Load Mode Register
AT91C_SDRAMC_MODE_DEEP_CMD EQU (0x6) ;- (SDRAMC) Enter Deep Power Mode
;- -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
AT91C_SDRAMC_COUNT EQU (0xFFF:SHL:0) ;- (SDRAMC) Refresh Counter
;- -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
AT91C_SDRAMC_NC EQU (0x3:SHL:0) ;- (SDRAMC) Number of Column Bits
AT91C_SDRAMC_NC_8 EQU (0x0) ;- (SDRAMC) 8 Bits
AT91C_SDRAMC_NC_9 EQU (0x1) ;- (SDRAMC) 9 Bits
AT91C_SDRAMC_NC_10 EQU (0x2) ;- (SDRAMC) 10 Bits
AT91C_SDRAMC_NC_11 EQU (0x3) ;- (SDRAMC) 11 Bits
AT91C_SDRAMC_NR EQU (0x3:SHL:2) ;- (SDRAMC) Number of Row Bits
AT91C_SDRAMC_NR_11 EQU (0x0:SHL:2) ;- (SDRAMC) 11 Bits
AT91C_SDRAMC_NR_12 EQU (0x1:SHL:2) ;- (SDRAMC) 12 Bits
AT91C_SDRAMC_NR_13 EQU (0x2:SHL:2) ;- (SDRAMC) 13 Bits
AT91C_SDRAMC_NB EQU (0x1:SHL:4) ;- (SDRAMC) Number of Banks
AT91C_SDRAMC_NB_2_BANKS EQU (0x0:SHL:4) ;- (SDRAMC) 2 banks
AT91C_SDRAMC_NB_4_BANKS EQU (0x1:SHL:4) ;- (SDRAMC) 4 banks
AT91C_SDRAMC_CAS EQU (0x3:SHL:5) ;- (SDRAMC) CAS Latency
AT91C_SDRAMC_CAS_2 EQU (0x2:SHL:5) ;- (SDRAMC) 2 cycles
AT91C_SDRAMC_CAS_3 EQU (0x3:SHL:5) ;- (SDRAMC) 3 cycles
AT91C_SDRAMC_DBW EQU (0x1:SHL:7) ;- (SDRAMC) Data Bus Width
AT91C_SDRAMC_DBW_32_BITS EQU (0x0:SHL:7) ;- (SDRAMC) 32 Bits datas bus
AT91C_SDRAMC_DBW_16_BITS EQU (0x1:SHL:7) ;- (SDRAMC) 16 Bits datas bus
AT91C_SDRAMC_TWR EQU (0xF:SHL:8) ;- (SDRAMC) Number of Write Recovery Time Cycles
AT91C_SDRAMC_TWR_0 EQU (0x0:SHL:8) ;- (SDRAMC) Value : 0
AT91C_SDRAMC_TWR_1 EQU (0x1:SHL:8) ;- (SDRAMC) Value : 1
AT91C_SDRAMC_TWR_2 EQU (0x2:SHL:8) ;- (SDRAMC) Value : 2
AT91C_SDRAMC_TWR_3 EQU (0x3:SHL:8) ;- (SDRAMC) Value : 3
AT91C_SDRAMC_TWR_4 EQU (0x4:SHL:8) ;- (SDRAMC) Value : 4
AT91C_SDRAMC_TWR_5 EQU (0x5:SHL:8) ;- (SDRAMC) Value : 5
AT91C_SDRAMC_TWR_6 EQU (0x6:SHL:8) ;- (SDRAMC) Value : 6
AT91C_SDRAMC_TWR_7 EQU (0x7:SHL:8) ;- (SDRAMC) Value : 7
AT91C_SDRAMC_TWR_8 EQU (0x8:SHL:8) ;- (SDRAMC) Value : 8
AT91C_SDRAMC_TWR_9 EQU (0x9:SHL:8) ;- (SDRAMC) Value : 9
AT91C_SDRAMC_TWR_10 EQU (0xA:SHL:8) ;- (SDRAMC) Value : 10
AT91C_SDRAMC_TWR_11 EQU (0xB:SHL:8) ;- (SDRAMC) Value : 11
AT91C_SDRAMC_TWR_12 EQU (0xC:SHL:8) ;- (SDRAMC) Value : 12
AT91C_SDRAMC_TWR_13 EQU (0xD:SHL:8) ;- (SDRAMC) Value : 13
AT91C_SDRAMC_TWR_14 EQU (0xE:SHL:8) ;- (SDRAMC) Value : 14
AT91C_SDRAMC_TWR_15 EQU (0xF:SHL:8) ;- (SDRAMC) Value : 15
AT91C_SDRAMC_TRC EQU (0xF:SHL:12) ;- (SDRAMC) Number of RAS Cycle Time Cycles
AT91C_SDRAMC_TRC_0 EQU (0x0:SHL:12) ;- (SDRAMC) Value : 0
AT91C_SDRAMC_TRC_1 EQU (0x1:SHL:12) ;- (SDRAMC) Value : 1
AT91C_SDRAMC_TRC_2 EQU (0x2:SHL:12) ;- (SDRAMC) Value : 2
AT91C_SDRAMC_TRC_3 EQU (0x3:SHL:12) ;- (SDRAMC) Value : 3
AT91C_SDRAMC_TRC_4 EQU (0x4:SHL:12) ;- (SDRAMC) Value : 4
AT91C_SDRAMC_TRC_5 EQU (0x5:SHL:12) ;- (SDRAMC) Value : 5
AT91C_SDRAMC_TRC_6 EQU (0x6:SHL:12) ;- (SDRAMC) Value : 6
AT91C_SDRAMC_TRC_7 EQU (0x7:SHL:12) ;- (SDRAMC) Value : 7
AT91C_SDRAMC_TRC_8 EQU (0x8:SHL:12) ;- (SDRAMC) Value : 8
AT91C_SDRAMC_TRC_9 EQU (0x9:SHL:12) ;- (SDRAMC) Value : 9
AT91C_SDRAMC_TRC_10 EQU (0xA:SHL:12) ;- (SDRAMC) Value : 10
AT91C_SDRAMC_TRC_11 EQU (0xB:SHL:12) ;- (SDRAMC) Value : 11
AT91C_SDRAMC_TRC_12 EQU (0xC:SHL:12) ;- (SDRAMC) Value : 12
AT91C_SDRAMC_TRC_13 EQU (0xD:SHL:12) ;- (SDRAMC) Value : 13
AT91C_SDRAMC_TRC_14 EQU (0xE:SHL:12) ;- (SDRAMC) Value : 14
AT91C_SDRAMC_TRC_15 EQU (0xF:SHL:12) ;- (SDRAMC) Value : 15
AT91C_SDRAMC_TRP EQU (0xF:SHL:16) ;- (SDRAMC) Number of RAS Precharge Time Cycles
AT91C_SDRAMC_TRP_0 EQU (0x0:SHL:16) ;- (SDRAMC) Value : 0
AT91C_SDRAMC_TRP_1 EQU (0x1:SHL:16) ;- (SDRAMC) Value : 1
AT91C_SDRAMC_TRP_2 EQU (0x2:SHL:16) ;- (SDRAMC) Value : 2
AT91C_SDRAMC_TRP_3 EQU (0x3:SHL:16) ;- (SDRAMC) Value : 3
AT91C_SDRAMC_TRP_4 EQU (0x4:SHL:16) ;- (SDRAMC) Value : 4
AT91C_SDRAMC_TRP_5 EQU (0x5:SHL:16) ;- (SDRAMC) Value : 5
AT91C_SDRAMC_TRP_6 EQU (0x6:SHL:16) ;- (SDRAMC) Value : 6
AT91C_SDRAMC_TRP_7 EQU (0x7:SHL:16) ;- (SDRAMC) Value : 7
AT91C_SDRAMC_TRP_8 EQU (0x8:SHL:16) ;- (SDRAMC) Value : 8
AT91C_SDRAMC_TRP_9 EQU (0x9:SHL:16) ;- (SDRAMC) Value : 9
AT91C_SDRAMC_TRP_10 EQU (0xA:SHL:16) ;- (SDRAMC) Value : 10
AT91C_SDRAMC_TRP_11 EQU (0xB:SHL:16) ;- (SDRAMC) Value : 11
AT91C_SDRAMC_TRP_12 EQU (0xC:SHL:16) ;- (SDRAMC) Value : 12
AT91C_SDRAMC_TRP_13 EQU (0xD:SHL:16) ;- (SDRAMC) Value : 13
AT91C_SDRAMC_TRP_14 EQU (0xE:SHL:16) ;- (SDRAMC) Value : 14
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