at91sam9260_sys.html

ATMEL AT91SAM9260的中段控制程序！

<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x44C</b></font></td><td><font size="-1"><a href="#MATRIX_SCFG3">MATRIX_SCFG3</a></font></td><td><font size="-1"> Slave Configuration Register 3 (ebi)</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x450</b></font></td><td><font size="-1"><a href="#MATRIX_SCFG4">MATRIX_SCFG4</a></font></td><td><font size="-1"> Slave Configuration Register 4 (bridge)    </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x480</b></font></td><td><font size="-1"><a href="#MATRIX_PRAS0">MATRIX_PRAS0</a></font></td><td><font size="-1"> PRAS0 (ram0) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x484</b></font></td><td><font size="-1"><a href="#MATRIX_PRBS0">MATRIX_PRBS0</a></font></td><td><font size="-1"> PRBS0 (ram0) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x488</b></font></td><td><font size="-1"><a href="#MATRIX_PRAS1">MATRIX_PRAS1</a></font></td><td><font size="-1"> PRAS1 (ram1) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x48C</b></font></td><td><font size="-1"><a href="#MATRIX_PRBS1">MATRIX_PRBS1</a></font></td><td><font size="-1"> PRBS1 (ram1) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x490</b></font></td><td><font size="-1"><a href="#MATRIX_PRAS2">MATRIX_PRAS2</a></font></td><td><font size="-1"> PRAS2 (ram2) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x494</b></font></td><td><font size="-1"><a href="#MATRIX_PRBS2">MATRIX_PRBS2</a></font></td><td><font size="-1"> PRBS2 (ram2) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x500</b></font></td><td><font size="-1"><a href="#MATRIX_MRCR">MATRIX_MRCR</a></font></td><td><font size="-1"> Master Remp Control Register </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x51C</b></font></td><td><font size="-1"><a href="#CCFG_EBICSA">CCFG_EBICSA</a></font></td><td><font size="-1"> EBI Chip Select Assignement Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x52C</b></font></td><td><font size="-1"><a href="#MATRIX_TEAKCFG">MATRIX_TEAKCFG</a></font></td><td><font size="-1"> Slave 7 (teak_prog) Special Function Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x5FC</b></font></td><td><font size="-1"><a href="#CCFG_MATRIXVERSION">CCFG_MATRIXVERSION</a></font></td><td><font size="-1"> Version Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x600</b></font></td><td><font size="-1">AIC_SMR[32] (<a href="#AIC_SMR">AIC_SMR</a>)</font></td><td><font size="-1">Source Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x680</b></font></td><td><font size="-1">AIC_SVR[32] (<a href="#AIC_SVR">AIC_SVR</a>)</font></td><td><font size="-1">Source Vector Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x700</b></font></td><td><font size="-1"><a href="#AIC_IVR">AIC_IVR</a></font></td><td><font size="-1">IRQ Vector Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x704</b></font></td><td><font size="-1"><a href="#AIC_FVR">AIC_FVR</a></font></td><td><font size="-1">FIQ Vector Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x708</b></font></td><td><font size="-1"><a href="#AIC_ISR">AIC_ISR</a></font></td><td><font size="-1">Interrupt Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x70C</b></font></td><td><font size="-1"><a href="#AIC_IPR">AIC_IPR</a></font></td><td><font size="-1">Interrupt Pending Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x710</b></font></td><td><font size="-1"><a href="#AIC_IMR">AIC_IMR</a></font></td><td><font size="-1">Interrupt Mask Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x714</b></font></td><td><font size="-1"><a href="#AIC_CISR">AIC_CISR</a></font></td><td><font size="-1">Core Interrupt Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x720</b></font></td><td><font size="-1"><a href="#AIC_IECR">AIC_IECR</a></font></td><td><font size="-1">Interrupt Enable Command Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x724</b></font></td><td><font size="-1"><a href="#AIC_IDCR">AIC_IDCR</a></font></td><td><font size="-1">Interrupt Disable Command Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x728</b></font></td><td><font size="-1"><a href="#AIC_ICCR">AIC_ICCR</a></font></td><td><font size="-1">Interrupt Clear Command Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x72C</b></font></td><td><font size="-1"><a href="#AIC_ISCR">AIC_ISCR</a></font></td><td><font size="-1">Interrupt Set Command Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x730</b></font></td><td><font size="-1"><a href="#AIC_EOICR">AIC_EOICR</a></font></td><td><font size="-1">End of Interrupt Command Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x734</b></font></td><td><font size="-1"><a href="#AIC_SPU">AIC_SPU</a></font></td><td><font size="-1">Spurious Vector Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x738</b></font></td><td><font size="-1"><a href="#AIC_DCR">AIC_DCR</a></font></td><td><font size="-1">Debug Control Register (Protect)</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x740</b></font></td><td><font size="-1"><a href="#AIC_FFER">AIC_FFER</a></font></td><td><font size="-1">Fast Forcing Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x744</b></font></td><td><font size="-1"><a href="#AIC_FFDR">AIC_FFDR</a></font></td><td><font size="-1">Fast Forcing Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x748</b></font></td><td><font size="-1"><a href="#AIC_FFSR">AIC_FFSR</a></font></td><td><font size="-1">Fast Forcing Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x800</b></font></td><td><font size="-1"><a href="AT91SAM9260_DBGU.html#DBGU_CR">DBGU_CR</a></font></td><td><font size="-1">Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x804</b></font></td><td><font size="-1"><a href="AT91SAM9260_DBGU.html#DBGU_MR">DBGU_MR</a></font></td><td><font size="-1">Mode Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x808</b></font></td><td><font size="-1"><a href="AT91SAM9260_DBGU.html#DBGU_IER">DBGU_IER</a></font></td><td><font size="-1">Interrupt Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x80C</b></font></td><td><font size="-1"><a href="AT91SAM9260_DBGU.html#DBGU_IDR">DBGU_IDR</a></font></td><td><font size="-1">Interrupt Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x810</b></font></td><td><font size="-1"><a href="AT91SAM9260_DBGU.html#DBGU_IMR">DBGU_IMR</a></font></td><td><font size="-1">Interrupt Mask Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x814</b></font></td><td><font size="-1"><a href="AT91SAM9260_DBGU.html#DBGU_CSR">DBGU_CSR</a></font></td><td><font size="-1">Channel Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x818</b></font></td><td><font size="-1"><a href="AT91SAM9260_DBGU.html#DBGU_RHR">DBGU_RHR</a></font></td><td><font size="-1">Receiver Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x81C</b></font></td><td><font size="-1"><a href="AT91SAM9260_DBGU.html#DBGU_THR">DBGU_THR</a></font></td><td><font size="-1">Transmitter Holding Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x820</b></font></td><td><font size="-1"><a href="AT91SAM9260_DBGU.html#DBGU_BRGR">DBGU_BRGR</a></font></td><td><font size="-1">Baud Rate Generator Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x840</b></font></td><td><font size="-1"><a href="AT91SAM9260_DBGU.html#DBGU_CIDR">DBGU_CIDR</a></font></td><td><font size="-1">Chip ID Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x844</b></font></td><td><font size="-1"><a href="AT91SAM9260_DBGU.html#DBGU_EXID">DBGU_EXID</a></font></td><td><font size="-1">Chip ID Extension Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x848</b></font></td><td><font size="-1"><a href="AT91SAM9260_DBGU.html#DBGU_FNTR">DBGU_FNTR</a></font></td><td><font size="-1">Force NTRST Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x900</b></font></td><td><font size="-1">DBGU_RPR (<a href="AT91SAM9260_PDC.html#PDC_RPR">PDC_RPR</a>)</font></td><td><font size="-1">Receive Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x904</b></font></td><td><font size="-1">DBGU_RCR (<a href="AT91SAM9260_PDC.html#PDC_RCR">PDC_RCR</a>)</font></td><td><font size="-1">Receive Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x908</b></font></td><td><font size="-1">DBGU_TPR (<a href="AT91SAM9260_PDC.html#PDC_TPR">PDC_TPR</a>)</font></td><td><font size="-1">Transmit Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x90C</b></font></td><td><font size="-1">DBGU_TCR (<a href="AT91SAM9260_PDC.html#PDC_TCR">PDC_TCR</a>)</font></td><td><font size="-1">Transmit Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x910</b></font></td><td><font size="-1">DBGU_RNPR (<a href="AT91SAM9260_PDC.html#PDC_RNPR">PDC_RNPR</a>)</font></td><td><font size="-1">Receive Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x914</b></font></td><td><font size="-1">DBGU_RNCR (<a href="AT91SAM9260_PDC.html#PDC_RNCR">PDC_RNCR</a>)</font></td><td><font size="-1">Receive Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x918</b></font></td><td><font size="-1">DBGU_TNPR (<a href="AT91SAM9260_PDC.html#PDC_TNPR">PDC_TNPR</a>)</font></td><td><font size="-1">Transmit Next Pointer Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x91C</b></font></td><td><font size="-1">DBGU_TNCR (<a href="AT91SAM9260_PDC.html#PDC_TNCR">PDC_TNCR</a>)</font></td><td><font size="-1">Transmit Next Counter Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x920</b></font></td><td><font size="-1">DBGU_PTCR (<a href="AT91SAM9260_PDC.html#PDC_PTCR">PDC_PTCR</a>)</font></td><td><font size="-1">PDC Transfer Control Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x924</b></font></td><td><font size="-1">DBGU_PTSR (<a href="AT91SAM9260_PDC.html#PDC_PTSR">PDC_PTSR</a>)</font></td><td><font size="-1">PDC Transfer Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xA00</b></font></td><td><font size="-1">PIOA_PER (<a href="#PIO_PER">PIO_PER</a>)</font></td><td><font size="-1">PIO Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xA04</b></font></td><td><font size="-1">PIOA_PDR (<a href="#PIO_PDR">PIO_PDR</a>)</font></td><td><font size="-1">PIO Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xA08</b></font></td><td><font size="-1">PIOA_PSR (<a href="#PIO_PSR">PIO_PSR</a>)</font></td><td><font size="-1">PIO Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xA10</b></font></td><td><font size="-1">PIOA_OER (<a href="#PIO_OER">PIO_OER</a>)</font></td><td><font size="-1">Output Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xA14</b></font></td><td><font size="-1">PIOA_ODR (<a href="#PIO_ODR">PIO_ODR</a>)</font></td><td><font size="-1">Output Disable Registerr</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xA18</b></font></td><td><font size="-1">PIOA_OSR (<a href="#PIO_OSR">PIO_OSR</a>)</font></td><td><font size="-1">Output Status Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xA20</b></font></td><td><font size="-1">PIOA_IFER (<a href="#PIO_IFER">PIO_IFER</a>)</font></td><td><font size="-1">Input Filter Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xA24</b></font></td><td><font size="-1">PIOA_IFDR (<a href="#PIO_IFDR">PIO_IFDR</a>)</font></td><td><font size="-1">Input Filter Disable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xA28</b></font></td><td><font size="-1">PIOA_IFSR (<a href="#PIO_IFSR">PIO_IFSR</a>)</font></td><td><font size="-1">Input Filter Status Register</font></td></tr>