at91sam9260_pmc.html

ATMEL AT91SAM9260的中段控制程序！

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<a name="CKGR_PLLAR"></a><h4><a href="#PMC">PMC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> CKGR_PLLAR  <i>PLL A Register</i></h4><ul><null><font size="-2"><li><b>PMC</b> <i><a href="AT91SAM9260_h.html#AT91C_PMC_PLLAR">AT91C_PMC_PLLAR</a></i> 0xFFFFFC28</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="CKGR_DIVA"></a><b>CKGR_DIVA</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_DIVA">AT91C_CKGR_DIVA</a></font></td><td><b>Divider A Selected</b><br>2-255 Divider output is the selected clock divided by DIVA<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_DIVA_0"></a><b>CKGR_DIVA_0</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_DIVA_0">AT91C_CKGR_DIVA_0</a></font></td><td><br>Divider A output is 0</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_DIVA_BYPASS"></a><b>CKGR_DIVA_BYPASS</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_DIVA_BYPASS">AT91C_CKGR_DIVA_BYPASS</a></font></td><td><br>Divider A is bypassed</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">13..8</td><td align="CENTER"><a name="CKGR_PLLACOUNT"></a><b>CKGR_PLLACOUNT</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_PLLACOUNT">AT91C_CKGR_PLLACOUNT</a></font></td><td><b>PLL A Counter</b><br>Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after PMC_PLLA is written.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="CKGR_OUTA"></a><b>CKGR_OUTA</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_OUTA">AT91C_CKGR_OUTA</a></font></td><td><b>PLL A Output Frequency Range</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_OUTA_0"></a><b>CKGR_OUTA_0</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_OUTA_0">AT91C_CKGR_OUTA_0</a></font></td><td><br>Please refer to the PLLA datasheet</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_OUTA_1"></a><b>CKGR_OUTA_1</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_OUTA_1">AT91C_CKGR_OUTA_1</a></font></td><td><br>Please refer to the PLLA datasheet</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="CKGR_OUTA_2"></a><b>CKGR_OUTA_2</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_OUTA_2">AT91C_CKGR_OUTA_2</a></font></td><td><br>Please refer to the PLLA datasheet</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="CKGR_OUTA_3"></a><b>CKGR_OUTA_3</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_OUTA_3">AT91C_CKGR_OUTA_3</a></font></td><td><br>Please refer to the PLLA datasheet</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">26..16</td><td align="CENTER"><a name="CKGR_MULA"></a><b>CKGR_MULA</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_MULA">AT91C_CKGR_MULA</a></font></td><td><b>PLL A Multiplier</b><br>0 = The PLL A is deactivated.<br>1 up to 2047 = The PLL A output frequency is the PLL A input frequency multiplied by MULA + 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">29</td><td align="CENTER"><a name="CKGR_SRCA"></a><b>CKGR_SRCA</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_SRCA">AT91C_CKGR_SRCA</a></font></td><td><b></b><br>BE CAREFUL !!! This bit MUST BE SET TO 1.</td></tr>
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<a name="CKGR_PLLBR"></a><h4><a href="#PMC">PMC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> CKGR_PLLBR  <i>PLL B Register</i></h4><ul><null><font size="-2"><li><b>PMC</b> <i><a href="AT91SAM9260_h.html#AT91C_PMC_PLLBR">AT91C_PMC_PLLBR</a></i> 0xFFFFFC2C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="CKGR_DIVB"></a><b>CKGR_DIVB</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_DIVB">AT91C_CKGR_DIVB</a></font></td><td><b>Divider B Selected</b><br>2-255 Divider output is the selected clock divided by DIVB<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_DIVB_0"></a><b>CKGR_DIVB_0</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_DIVB_0">AT91C_CKGR_DIVB_0</a></font></td><td><br>Divider B output is 0</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_DIVB_BYPASS"></a><b>CKGR_DIVB_BYPASS</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_DIVB_BYPASS">AT91C_CKGR_DIVB_BYPASS</a></font></td><td><br>Divider B is bypassed</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">13..8</td><td align="CENTER"><a name="CKGR_PLLBCOUNT"></a><b>CKGR_PLLBCOUNT</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_PLLBCOUNT">AT91C_CKGR_PLLBCOUNT</a></font></td><td><b>PLL B Counter</b><br>Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after PMC_PLLB is written.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="CKGR_OUTB"></a><b>CKGR_OUTB</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_OUTB">AT91C_CKGR_OUTB</a></font></td><td><b>PLL B Output Frequency Range</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_OUTB_0"></a><b>CKGR_OUTB_0</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_OUTB_0">AT91C_CKGR_OUTB_0</a></font></td><td><br>Please refer to the PLLB datasheet</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_OUTB_1"></a><b>CKGR_OUTB_1</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_OUTB_1">AT91C_CKGR_OUTB_1</a></font></td><td><br>Please refer to the PLLB datasheet</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="CKGR_OUTB_2"></a><b>CKGR_OUTB_2</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_OUTB_2">AT91C_CKGR_OUTB_2</a></font></td><td><br>Please refer to the PLLB datasheet</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="CKGR_OUTB_3"></a><b>CKGR_OUTB_3</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_OUTB_3">AT91C_CKGR_OUTB_3</a></font></td><td><br>Please refer to the PLLB datasheet</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">26..16</td><td align="CENTER"><a name="CKGR_MULB"></a><b>CKGR_MULB</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_MULB">AT91C_CKGR_MULB</a></font></td><td><b>PLL B Multiplier</b><br>0 = The PLL B is deactivated.<br>1 up to 2047 = The PLL B output frequency is the PLL B input frequency multiplied by MULB + 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">29..28</td><td align="CENTER"><a name="CKGR_USBDIV"></a><b>CKGR_USBDIV</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_USBDIV">AT91C_CKGR_USBDIV</a></font></td><td><b>Divider for USB Clocks</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_USBDIV_0"></a><b>CKGR_USBDIV_0</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_USBDIV_0">AT91C_CKGR_USBDIV_0</a></font></td><td><br>Divider output is PLL clock output</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_USBDIV_1"></a><b>CKGR_USBDIV_1</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_USBDIV_1">AT91C_CKGR_USBDIV_1</a></font></td><td><br>Divider output is PLL clock output divided by 2</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="CKGR_USBDIV_2"></a><b>CKGR_USBDIV_2</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_CKGR_USBDIV_2">AT91C_CKGR_USBDIV_2</a></font></td><td><br>Divider output is PLL clock output divided by 4</td></tr>
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<a name="PMC_MCKR"></a><h4><a href="#PMC">PMC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> PMC_MCKR  <i>Master Clock Register</i></h4><ul><null><font size="-2"><li><b>PMC</b> <i><a href="AT91SAM9260_h.html#AT91C_PMC_MCKR">AT91C_PMC_MCKR</a></i> 0xFFFFFC30</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">1..0</td><td align="CENTER"><a name="PMC_CSS"></a><b>PMC_CSS</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_PMC_CSS">AT91C_PMC_CSS</a></font></td><td><b>Programmable Clock Selection</b><br>Clock selection<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="PMC_CSS_SLOW_CLK"></a><b>PMC_CSS_SLOW_CLK</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_CSS_SLOW_CLK">AT91C_PMC_CSS_SLOW_CLK</a></font></td><td><br>Slow Clock is selected</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="PMC_CSS_MAIN_CLK"></a><b>PMC_CSS_MAIN_CLK</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_CSS_MAIN_CLK">AT91C_PMC_CSS_MAIN_CLK</a></font></td><td><br>Main Clock is selected</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="PMC_CSS_PLLA_CLK"></a><b>PMC_CSS_PLLA_CLK</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_CSS_PLLA_CLK">AT91C_PMC_CSS_PLLA_CLK</a></font></td><td><br>Clock from PLL A is selected</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="PMC_CSS_PLLB_CLK"></a><b>PMC_CSS_PLLB_CLK</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_CSS_PLLB_CLK">AT91C_PMC_CSS_PLLB_CLK</a></font></td><td><br>Clock from PLL B is selected</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">4..2</td><td align="CENTER"><a name="PMC_PRES"></a><b>PMC_PRES</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_PMC_PRES">AT91C_PMC_PRES</a></font></td><td><b>Programmable Clock Prescaler</b><br>Master clock<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="PMC_PRES_CLK"></a><b>PMC_PRES_CLK</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_PRES_CLK">AT91C_PMC_PRES_CLK</a></font></td><td><br>Selected clock</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="PMC_PRES_CLK_2"></a><b>PMC_PRES_CLK_2</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_PRES_CLK_2">AT91C_PMC_PRES_CLK_2</a></font></td><td><br>Selected clock divided by 2</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="PMC_PRES_CLK_4"></a><b>PMC_PRES_CLK_4</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_PRES_CLK_4">AT91C_PMC_PRES_CLK_4</a></font></td><td><br>Selected clock divided by 4</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="PMC_PRES_CLK_8"></a><b>PMC_PRES_CLK_8</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_PRES_CLK_8">AT91C_PMC_PRES_CLK_8</a></font></td><td><br>Selected clock divided by 8</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="PMC_PRES_CLK_16"></a><b>PMC_PRES_CLK_16</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_PRES_CLK_16">AT91C_PMC_PRES_CLK_16</a></font></td><td><br>Selected clock divided by 16</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="PMC_PRES_CLK_32"></a><b>PMC_PRES_CLK_32</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_PRES_CLK_32">AT91C_PMC_PRES_CLK_32</a></font></td><td><br>Selected clock divided by 32</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="PMC_PRES_CLK_64"></a><b>PMC_PRES_CLK_64</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_PRES_CLK_64">AT91C_PMC_PRES_CLK_64</a></font></td><td><br>Selected clock divided by 64</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">9..8</td><td align="CENTER"><a name="PMC_MDIV"></a><b>PMC_MDIV</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_PMC_MDIV">AT91C_PMC_MDIV</a></font></td><td><b>Master Clock Division</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="PMC_MDIV_1"></a><b>PMC_MDIV_1</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_MDIV_1">AT91C_PMC_MDIV_1</a></font></td><td><br>The master clock and the processor clock are the same</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="PMC_MDIV_2"></a><b>PMC_MDIV_2</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_MDIV_2">AT91C_PMC_MDIV_2</a></font></td><td><br>The processor clock is twice as fast as the master clock</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="PMC_MDIV_3"></a><b>PMC_MDIV_3</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_PMC_MDIV_3">AT91C_PMC_MDIV_3</a></font></td><td><br>The processor clock is four times faster than the master clock</td></tr>