at91sam9260_matrix.html

ATMEL AT91SAM9260的中段控制程序！

<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM9260_h.html#AT91F_MATRIX_EnableTEAK">AT91F_MATRIX_EnableTEAK</a></b></font></td><td><font size="-1">Activate the TEAK DSP core</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM9260_h.html#AT91F_MATRIX_TEAKBootRoutineEnable">AT91F_MATRIX_TEAKBootRoutineEnable</a></b></font></td><td><font size="-1">Boot from TEAK's boot routine</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM9260_h.html#AT91F_MATRIX_TEAKProgramMemoryAccessEnabled">AT91F_MATRIX_TEAKProgramMemoryAccessEnabled</a></b></font></td><td><font size="-1">Access from AHB to TEAK's program memory enabled</font></td></tr>
</null></table></null><h2>MATRIX Register Description</h2>
<null><a name="MATRIX_MCFG0"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG0  <i> Master Configuration Register 0 (ram96k)     </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG0">AT91C_MATRIX_MCFG0</a></i> 0xFFFFEE00</font></null></ul><a name="MATRIX_MCFG1"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG1  <i> Master Configuration Register 1 (rom)    </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG1">AT91C_MATRIX_MCFG1</a></i> 0xFFFFEE04</font></null></ul><a name="MATRIX_MCFG2"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG2  <i> Master Configuration Register 2 (hperiphs) </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG2">AT91C_MATRIX_MCFG2</a></i> 0xFFFFEE08</font></null></ul><a name="MATRIX_MCFG3"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG3  <i> Master Configuration Register 3 (ebi)</i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG3">AT91C_MATRIX_MCFG3</a></i> 0xFFFFEE0C</font></null></ul><a name="MATRIX_MCFG4"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG4  <i> Master Configuration Register 4 (bridge)    </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG4">AT91C_MATRIX_MCFG4</a></i> 0xFFFFEE10</font></null></ul><a name="MATRIX_MCFG5"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG5  <i> Master Configuration Register 5 (mailbox)    </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG5">AT91C_MATRIX_MCFG5</a></i> 0xFFFFEE14</font></null></ul><a name="MATRIX_MCFG6"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG6  <i> Master Configuration Register 6 (ram16k)  </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG6">AT91C_MATRIX_MCFG6</a></i> 0xFFFFEE18</font></null></ul><a name="MATRIX_MCFG7"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG7  <i> Master Configuration Register 7 (teak_prog)     </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG7">AT91C_MATRIX_MCFG7</a></i> 0xFFFFEE1C</font></null></ul><a name="MATRIX_SCFG0"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_SCFG0  <i> Slave Configuration Register 0 (ram96k)     </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_SCFG0">AT91C_MATRIX_SCFG0</a></i> 0xFFFFEE40</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="MATRIX_SLOT_CYCLE"></a><b>MATRIX_SLOT_CYCLE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_SLOT_CYCLE">AT91C_MATRIX_SLOT_CYCLE</a></font></td><td><b>Maximum Number of Allowed Cycles for a Burst</b><br>When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.<br>This limit has been placed to avoid locking very slow slave when very long burst are used.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17..16</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE"></a><b>MATRIX_DEFMSTR_TYPE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE">AT91C_MATRIX_DEFMSTR_TYPE</a></font></td><td><b>Default Master Type</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE_NO_DEFMSTR"></a><b>MATRIX_DEFMSTR_TYPE_NO_DEFMSTR</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR">AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR</a></font></td><td><br>No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR"></a><b>MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR">AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR</a></font></td><td><br>Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR"></a><b>MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR">AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR</a></font></td><td><br>Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">20..18</td><td align="CENTER"><a name="MATRIX_FIXED_DEFMSTR0"></a><b>MATRIX_FIXED_DEFMSTR0</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_FIXED_DEFMSTR0">AT91C_MATRIX_FIXED_DEFMSTR0</a></font></td><td><b>Fixed Index of Default Master</b><br>This is the index of the Fixed Default Master for this slave<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="MATRIX_FIXED_DEFMSTR0_ARM926I"></a><b>MATRIX_FIXED_DEFMSTR0_ARM926I</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I">AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I</a></font></td><td><br>ARM926EJ-S Instruction Master is Default Master</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="MATRIX_FIXED_DEFMSTR0_ARM926D"></a><b>MATRIX_FIXED_DEFMSTR0_ARM926D</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D">AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D</a></font></td><td><br>ARM926EJ-S Data Master is Default Master</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="MATRIX_FIXED_DEFMSTR0_HPDC3"></a><b>MATRIX_FIXED_DEFMSTR0_HPDC3</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3">AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3</a></font></td><td><br>HPDC3 Master is Default Master</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="MATRIX_FIXED_DEFMSTR0_LCDC"></a><b>MATRIX_FIXED_DEFMSTR0_LCDC</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_FIXED_DEFMSTR0_LCDC">AT91C_MATRIX_FIXED_DEFMSTR0_LCDC</a></font></td><td><br>LCDC Master is Default Master</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="MATRIX_FIXED_DEFMSTR0_DMA"></a><b>MATRIX_FIXED_DEFMSTR0_DMA</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_FIXED_DEFMSTR0_DMA">AT91C_MATRIX_FIXED_DEFMSTR0_DMA</a></font></td><td><br>DMA Master is Default Master</td></tr>
</null></table></font>
</td></tr>
</null></table>
<a name="MATRIX_SCFG1"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_SCFG1  <i> Slave Configuration Register 1 (rom)    </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_SCFG1">AT91C_MATRIX_SCFG1</a></i> 0xFFFFEE44</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="MATRIX_SLOT_CYCLE"></a><b>MATRIX_SLOT_CYCLE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_SLOT_CYCLE">AT91C_MATRIX_SLOT_CYCLE</a></font></td><td><b>Maximum Number of Allowed Cycles for a Burst</b><br>When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.<br>This limit has been placed to avoid locking very slow slave when very long burst are used.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17..16</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE"></a><b>MATRIX_DEFMSTR_TYPE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE">AT91C_MATRIX_DEFMSTR_TYPE</a></font></td><td><b>Default Master Type</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE_NO_DEFMSTR"></a><b>MATRIX_DEFMSTR_TYPE_NO_DEFMSTR</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR">AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR</a></font></td><td><br>No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR"></a><b>MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR">AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR</a></font></td><td><br>Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR"></a><b>MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR">AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR</a></font></td><td><br>Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">20..18</td><td align="CENTER"><a name="MATRIX_FIXED_DEFMSTR1"></a><b>MATRIX_FIXED_DEFMSTR1</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_FIXED_DEFMSTR1">AT91C_MATRIX_FIXED_DEFMSTR1</a></font></td><td><b>Fixed Index of Default Master</b><br>This is the index of the Fixed Default Master for this slave<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="MATRIX_FIXED_DEFMSTR1_ARM926I"></a><b>MATRIX_FIXED_DEFMSTR1_ARM926I</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I">AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I</a></font></td><td><br>ARM926EJ-S Instruction Master is Default Master</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="MATRIX_FIXED_DEFMSTR1_ARM926D"></a><b>MATRIX_FIXED_DEFMSTR1_ARM926D</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D">AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D</a></font></td><td><br>ARM926EJ-S Data Master is Default Master</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="MATRIX_FIXED_DEFMSTR1_HPDC3"></a><b>MATRIX_FIXED_DEFMSTR1_HPDC3</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3">AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3</a></font></td><td><br>HPDC3 Master is Default Master</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="MATRIX_FIXED_DEFMSTR1_LCDC"></a><b>MATRIX_FIXED_DEFMSTR1_LCDC</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_FIXED_DEFMSTR1_LCDC">AT91C_MATRIX_FIXED_DEFMSTR1_LCDC</a></font></td><td><br>LCDC Master is Default Master</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="MATRIX_FIXED_DEFMSTR1_DMA"></a><b>MATRIX_FIXED_DEFMSTR1_DMA</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_FIXED_DEFMSTR1_DMA">AT91C_MATRIX_FIXED_DEFMSTR1_DMA</a></font></td><td><br>DMA Master is Default Master</td></tr>
</null></table></font>
</td></tr>
</null></table>
<a name="MATRIX_SCFG2"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_SCFG2  <i> Slave Configuration Register 2 (hperiphs) </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_SCFG2">AT91C_MATRIX_SCFG2</a></i> 0xFFFFEE48</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="MATRIX_SLOT_CYCLE"></a><b>MATRIX_SLOT_CYCLE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_SLOT_CYCLE">AT91C_MATRIX_SLOT_CYCLE</a></font></td><td><b>Maximum Number of Allowed Cycles for a Burst</b><br>When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.<br>This limit has been placed to avoid locking very slow slave when very long burst are used.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17..16</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE"></a><b>MATRIX_DEFMSTR_TYPE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE">AT91C_MATRIX_DEFMSTR_TYPE</a></font></td><td><b>Default Master Type</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE_NO_DEFMSTR"></a><b>MATRIX_DEFMSTR_TYPE_NO_DEFMSTR</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR">AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR</a></font></td><td><br>No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR"></a><b>MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR">AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR</a></font></td><td><br>Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR"></a><b>MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR">AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR</a></font></td><td><br>Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.</td></tr>