at91sam9260_emac.html

ATMEL AT91SAM9260的中段控制程序！

<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="EMAC_ROVR"></a><b>EMAC_ROVR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_ROVR">AT91C_EMAC_ROVR</a></font></td><td><b></b><br>RX overrun. Set when the RX overrun status bit is set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="EMAC_HRESP"></a><b>EMAC_HRESP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_HRESP">AT91C_EMAC_HRESP</a></font></td><td><b></b><br>HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="EMAC_PFRE"></a><b>EMAC_PFRE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_PFRE">AT91C_EMAC_PFRE</a></font></td><td><b></b><br>Indicates a valid pause has been received. Cleared on a read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="EMAC_PTZ"></a><b>EMAC_PTZ</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_PTZ">AT91C_EMAC_PTZ</a></font></td><td><b></b><br>set when the pause time register, 0x38 decrements to zero. Cleared on a read.</td></tr>
</null></table>
<a name="EMAC_IDR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_IDR  <i>Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_IDR">AT91C_EMACB_IDR</a></i> 0xFFFC402C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_MFD"></a><b>EMAC_MFD</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_MFD">AT91C_EMAC_MFD</a></font></td><td><b></b><br>Management Frame done. The PHY maintenance register has completed its operation. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_RCOMP"></a><b>EMAC_RCOMP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RCOMP">AT91C_EMAC_RCOMP</a></font></td><td><b></b><br>Receive complete. A frame has been stored in memory. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_RXUBR"></a><b>EMAC_RXUBR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RXUBR">AT91C_EMAC_RXUBR</a></font></td><td><b></b><br>Receive Used Bit read. Set when a receive buffer descriptor is read with its used bit set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="EMAC_TXUBR"></a><b>EMAC_TXUBR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TXUBR">AT91C_EMAC_TXUBR</a></font></td><td><b></b><br>Transmit Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_TUNDR"></a><b>EMAC_TUNDR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TUNDR">AT91C_EMAC_TUNDR</a></font></td><td><b></b><br>Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_RLEX"></a><b>EMAC_RLEX</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RLEX">AT91C_EMAC_RLEX</a></font></td><td><b></b><br>Retry limit exceeded. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_TXERR"></a><b>EMAC_TXERR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TXERR">AT91C_EMAC_TXERR</a></font></td><td><b></b><br>Transmit buffers exhausted in mid-frame - transmit error. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="EMAC_TCOMP"></a><b>EMAC_TCOMP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TCOMP">AT91C_EMAC_TCOMP</a></font></td><td><b></b><br>Transmit complete. Set when a frame has been transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="EMAC_LINK"></a><b>EMAC_LINK</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_LINK">AT91C_EMAC_LINK</a></font></td><td><b></b><br>Set when LINK pin changes value. Optional.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="EMAC_ROVR"></a><b>EMAC_ROVR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_ROVR">AT91C_EMAC_ROVR</a></font></td><td><b></b><br>RX overrun. Set when the RX overrun status bit is set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="EMAC_HRESP"></a><b>EMAC_HRESP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_HRESP">AT91C_EMAC_HRESP</a></font></td><td><b></b><br>HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="EMAC_PFRE"></a><b>EMAC_PFRE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_PFRE">AT91C_EMAC_PFRE</a></font></td><td><b></b><br>Indicates a valid pause has been received. Cleared on a read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="EMAC_PTZ"></a><b>EMAC_PTZ</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_PTZ">AT91C_EMAC_PTZ</a></font></td><td><b></b><br>set when the pause time register, 0x38 decrements to zero. Cleared on a read.</td></tr>
</null></table>
<a name="EMAC_IMR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_IMR  <i>Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_IMR">AT91C_EMACB_IMR</a></i> 0xFFFC4030</font></null></ul><br>Important Note: The interrupt is masked (disabled) when the corresponding bit is set. This is non-standard for AT91 products as generally a mask bit set enables the interrupt.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_MFD"></a><b>EMAC_MFD</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_MFD">AT91C_EMAC_MFD</a></font></td><td><b></b><br>Management Frame done. The PHY maintenance register has completed its operation. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_RCOMP"></a><b>EMAC_RCOMP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RCOMP">AT91C_EMAC_RCOMP</a></font></td><td><b></b><br>Receive complete. A frame has been stored in memory. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_RXUBR"></a><b>EMAC_RXUBR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RXUBR">AT91C_EMAC_RXUBR</a></font></td><td><b></b><br>Receive Used Bit read. Set when a receive buffer descriptor is read with its used bit set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="EMAC_TXUBR"></a><b>EMAC_TXUBR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TXUBR">AT91C_EMAC_TXUBR</a></font></td><td><b></b><br>Transmit Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_TUNDR"></a><b>EMAC_TUNDR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TUNDR">AT91C_EMAC_TUNDR</a></font></td><td><b></b><br>Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_RLEX"></a><b>EMAC_RLEX</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RLEX">AT91C_EMAC_RLEX</a></font></td><td><b></b><br>Retry limit exceeded. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_TXERR"></a><b>EMAC_TXERR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TXERR">AT91C_EMAC_TXERR</a></font></td><td><b></b><br>Transmit buffers exhausted in mid-frame - transmit error. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="EMAC_TCOMP"></a><b>EMAC_TCOMP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TCOMP">AT91C_EMAC_TCOMP</a></font></td><td><b></b><br>Transmit complete. Set when a frame has been transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="EMAC_LINK"></a><b>EMAC_LINK</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_LINK">AT91C_EMAC_LINK</a></font></td><td><b></b><br>Set when LINK pin changes value. Optional.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="EMAC_ROVR"></a><b>EMAC_ROVR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_ROVR">AT91C_EMAC_ROVR</a></font></td><td><b></b><br>RX overrun. Set when the RX overrun status bit is set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="EMAC_HRESP"></a><b>EMAC_HRESP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_HRESP">AT91C_EMAC_HRESP</a></font></td><td><b></b><br>HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="EMAC_PFRE"></a><b>EMAC_PFRE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_PFRE">AT91C_EMAC_PFRE</a></font></td><td><b></b><br>Indicates a valid pause has been received. Cleared on a read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="EMAC_PTZ"></a><b>EMAC_PTZ</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_PTZ">AT91C_EMAC_PTZ</a></font></td><td><b></b><br>set when the pause time register, 0x38 decrements to zero. Cleared on a read.</td></tr>
</null></table>
<a name="EMAC_MAN"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_MAN  <i>PHY Maintenance Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_MAN">AT91C_EMACB_MAN</a></i> 0xFFFC4034</font></null></ul><br>Writing to this register starts the shift register that controls the serial connection to the PHY. On each shift cycle the MDIO pin becomes equal to the MSB of the shift register and LSB of the shift register becomes equal to the value of the MDIO pin. When the shifting is complete an interrupt is generated and the IDLE field is set in the Network Status register.<br>When read, gives current shifted value.<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">15..0</td><td align="CENTER"><a name="EMAC_DATA"></a><b>EMAC_DATA</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_DATA">AT91C_EMAC_DATA</a></font></td><td><b></b><br>For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17..16</td><td align="CENTER"><a name="EMAC_CODE"></a><b>EMAC_CODE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_CODE">AT91C_EMAC_CODE</a></font></td><td><b></b><br>Must be written to 10 in accordance with IEEE standard 802.3. Reads as written.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">22..18</td><td align="CENTER"><a name="EMAC_REGA"></a><b>EMAC_REGA</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_REGA">AT91C_EMAC_REGA</a></font></td><td><b></b><br>Register address. Specifies the register in the PHY to access.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">27..23</td><td align="CENTER"><a name="EMAC_PHYA"></a><b>EMAC_PHYA</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_PHYA">AT91C_EMAC_PHYA</a></font></td><td><b></b><br>PHY address. Normally is 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">29..28</td><td align="CENTER"><a name="EMAC_RW"></a><b>EMAC_RW</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RW">AT91C_EMAC_RW</a></font></td><td><b></b><br>Read/write Operation. 10 is read. 01 is write. Any other value is an invalid PHY management frame.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31..30</td><td align="CENTER"><a name="EMAC_SOF"></a><b>EMAC_SOF</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_SOF">AT91C_EMAC_SOF</a></font></td><td><b></b><br>Must be written with 01 to make a valid PHY management frame. Conforms with IEEE standard 802.3.</td></tr>
</null></table>
<a name="EMAC_PTR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_PTR  <i>Pause Time Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_PTR">AT91C_EMACB_PTR</a></i> 0xFFFC4038</font></null></ul><br>16-Bit Register which stores the current value of the pause time register which is decremented every 512 bit time.<a name="EMAC_PFR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_PFR  <i>Pause Frames received Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_PFR">AT91C_EMACB_PFR</a></i> 0xFFFC403C</font></null></ul><br>A 16-bit register counting the number of good pause frames received.<a name="EMAC_FTO"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_FTO  <i>Frames Transmitted OK Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_FTO">AT91C_EMACB_FTO</a></i> 0xFFFC4040</font></null></ul><br>A 24-bit register counting the number of frames successfully transmitted.<a name="EMAC_SCF"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_SCF  <i>Single Collision Frame Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_SCF">AT91C_EMACB_SCF</a></i> 0xFFFC4044</font></null></ul><br>A 16-bit register counting the number of frames experiencing a single collision before being transmitted and experiencing no carrier loss nor underrun.<a name="EMAC_MCF"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_MCF  <i>Multiple Collision Frame Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_MCF">AT91C_EMACB_MCF</a></i> 0xFFFC4048</font></null></ul><br>A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no underrun).<a name="EMAC_FRO"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_FRO  <i>Frames Received OK Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_FRO">AT91C_EMACB_FRO</a></i> 0xFFFC404C</font></null></ul><br>A 24-bit register counting the number of good frames received, i.e., address recognized. A good frame is of length 64 to 1518 bytes and has no FCS, alignment or code errors.<a name="EMA