at91sam9260_emac.html

ATMEL AT91SAM9260的中段控制程序！

<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="EMAC_IRXFCS"></a><b>EMAC_IRXFCS</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_IRXFCS">AT91C_EMAC_IRXFCS</a></font></td><td><b>Ignore RX FCS</b><br>When set, frames with FCS/CRC errors are not rejected and no FCS error statistics are counted. For normal operation, this bit must be set to 0.</td></tr>
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<a name="EMAC_NSR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_NSR  <i>Network Status Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_NSR">AT91C_EMACB_NSR</a></i> 0xFFFC4008</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_LINKR"></a><b>EMAC_LINKR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_LINKR">AT91C_EMAC_LINKR</a></font></td><td><b></b><br>Reserved</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_MDIO"></a><b>EMAC_MDIO</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_MDIO">AT91C_EMAC_MDIO</a></font></td><td><b></b><br>0 = MDIO pin is not set<br>1 = MDIO pin set</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_IDLE"></a><b>EMAC_IDLE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_IDLE">AT91C_EMAC_IDLE</a></font></td><td><b></b><br>0 = PHY logic is idle<br>1 = PHY logic is running</td></tr>
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<a name="EMAC_TSR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_TSR  <i>Transmit Status Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_TSR">AT91C_EMACB_TSR</a></i> 0xFFFC4014</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_UBR"></a><b>EMAC_UBR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_UBR">AT91C_EMAC_UBR</a></font></td><td><b></b><br>Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_COL"></a><b>EMAC_COL</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_COL">AT91C_EMAC_COL</a></font></td><td><b></b><br>Collision occurred. Set by the assertion of collision. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_RLES"></a><b>EMAC_RLES</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RLES">AT91C_EMAC_RLES</a></font></td><td><b></b><br>Retry limit exceeded. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="EMAC_TGO"></a><b>EMAC_TGO</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TGO">AT91C_EMAC_TGO</a></font></td><td><b>Transmit Go</b><br>Transmit Go. If high transmit is active.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_BEX"></a><b>EMAC_BEX</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_BEX">AT91C_EMAC_BEX</a></font></td><td><b>Buffers exhausted mid frame</b><br>Buffers exhausted mid frame. if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and tx_er asserted. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_COMP"></a><b>EMAC_COMP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_COMP">AT91C_EMAC_COMP</a></font></td><td><b></b><br>Transmit complete. Set when a frame has been transmitted. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_UND"></a><b>EMAC_UND</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_UND">AT91C_EMAC_UND</a></font></td><td><b></b><br>Transmit underrun. Set when transmit DMA was not able to read data from memory in time. If this happens, the transmitter forces bad CRC. Cleared by writing a one to this bit.</td></tr>
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<a name="EMAC_RBQP"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_RBQP  <i>Receive Buffer Queue Pointer</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_RBQP">AT91C_EMACB_RBQP</a></i> 0xFFFC4018</font></null></ul><br>Receive buffer queue pointer. Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. The receive buffer is forced to word alignment.<a name="EMAC_TBQP"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_TBQP  <i>Transmit Buffer Queue Pointer</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_TBQP">AT91C_EMACB_TBQP</a></i> 0xFFFC401C</font></null></ul><br>Transmit buffer queue pointer.Written with the address of the start of the transmit queue, reads as a pointer to the first buffer of the frame being transmitted or about to be transmitted.<a name="EMAC_RSR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_RSR  <i>Receive Status Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_RSR">AT91C_EMACB_RSR</a></i> 0xFFFC4020</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_BNA"></a><b>EMAC_BNA</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_BNA">AT91C_EMAC_BNA</a></font></td><td><b></b><br>Buffer not available. An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_REC"></a><b>EMAC_REC</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_REC">AT91C_EMAC_REC</a></font></td><td><b></b><br>Frame received. One or more frames have been received and placed in memory. Cleared by writing a one to this bit.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_OVR"></a><b>EMAC_OVR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_OVR">AT91C_EMAC_OVR</a></font></td><td><b></b><br>RX overrun. The DMA block was unable to store the receive frame to memory, either because the ASB bus was not granted in time or because a not OK HRESP was returned. The buffer is recovered if this happens. Cleared by writing a one to this bit.</td></tr>
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<a name="EMAC_ISR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_ISR  <i>Interrupt Status Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_ISR">AT91C_EMACB_ISR</a></i> 0xFFFC4024</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_MFD"></a><b>EMAC_MFD</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_MFD">AT91C_EMAC_MFD</a></font></td><td><b></b><br>Management Frame done. The PHY maintenance register has completed its operation. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_RCOMP"></a><b>EMAC_RCOMP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RCOMP">AT91C_EMAC_RCOMP</a></font></td><td><b></b><br>Receive complete. A frame has been stored in memory. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_RXUBR"></a><b>EMAC_RXUBR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RXUBR">AT91C_EMAC_RXUBR</a></font></td><td><b></b><br>Receive Used Bit read. Set when a receive buffer descriptor is read with its used bit set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="EMAC_TXUBR"></a><b>EMAC_TXUBR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TXUBR">AT91C_EMAC_TXUBR</a></font></td><td><b></b><br>Transmit Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_TUNDR"></a><b>EMAC_TUNDR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TUNDR">AT91C_EMAC_TUNDR</a></font></td><td><b></b><br>Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_RLEX"></a><b>EMAC_RLEX</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RLEX">AT91C_EMAC_RLEX</a></font></td><td><b></b><br>Retry limit exceeded. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_TXERR"></a><b>EMAC_TXERR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TXERR">AT91C_EMAC_TXERR</a></font></td><td><b></b><br>Transmit buffers exhausted in mid-frame - transmit error. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="EMAC_TCOMP"></a><b>EMAC_TCOMP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TCOMP">AT91C_EMAC_TCOMP</a></font></td><td><b></b><br>Transmit complete. Set when a frame has been transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="EMAC_LINK"></a><b>EMAC_LINK</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_LINK">AT91C_EMAC_LINK</a></font></td><td><b></b><br>Set when LINK pin changes value. Optional.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="EMAC_ROVR"></a><b>EMAC_ROVR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_ROVR">AT91C_EMAC_ROVR</a></font></td><td><b></b><br>RX overrun. Set when the RX overrun status bit is set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="EMAC_HRESP"></a><b>EMAC_HRESP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_HRESP">AT91C_EMAC_HRESP</a></font></td><td><b></b><br>HRESP not OK. Set when the DMA block sees HRESP not OK. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="EMAC_PFRE"></a><b>EMAC_PFRE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_PFRE">AT91C_EMAC_PFRE</a></font></td><td><b></b><br>Indicates a valid pause has been received. Cleared on a read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="EMAC_PTZ"></a><b>EMAC_PTZ</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_PTZ">AT91C_EMAC_PTZ</a></font></td><td><b></b><br>set when the pause time register, 0x38 decrements to zero. Cleared on a read.</td></tr>
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<a name="EMAC_IER"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_IER  <i>Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_IER">AT91C_EMACB_IER</a></i> 0xFFFC4028</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_MFD"></a><b>EMAC_MFD</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_MFD">AT91C_EMAC_MFD</a></font></td><td><b></b><br>Management Frame done. The PHY maintenance register has completed its operation. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_RCOMP"></a><b>EMAC_RCOMP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RCOMP">AT91C_EMAC_RCOMP</a></font></td><td><b></b><br>Receive complete. A frame has been stored in memory. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_RXUBR"></a><b>EMAC_RXUBR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RXUBR">AT91C_EMAC_RXUBR</a></font></td><td><b></b><br>Receive Used Bit read. Set when a receive buffer descriptor is read with its used bit set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="EMAC_TXUBR"></a><b>EMAC_TXUBR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TXUBR">AT91C_EMAC_TXUBR</a></font></td><td><b></b><br>Transmit Used Bit Read. Set when a transmit buffer descriptor is read with its used bit set. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_TUNDR"></a><b>EMAC_TUNDR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TUNDR">AT91C_EMAC_TUNDR</a></font></td><td><b></b><br>Transmit error. Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_RLEX"></a><b>EMAC_RLEX</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RLEX">AT91C_EMAC_RLEX</a></font></td><td><b></b><br>Retry limit exceeded. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_TXERR"></a><b>EMAC_TXERR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TXERR">AT91C_EMAC_TXERR</a></font></td><td><b></b><br>Transmit buffers exhausted in mid-frame - transmit error. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="EMAC_TCOMP"></a><b>EMAC_TCOMP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TCOMP">AT91C_EMAC_TCOMP</a></font></td><td><b></b><br>Transmit complete. Set when a frame has been transmitted. Cleared on read.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="EMAC_LINK"></a><b>EMAC_LINK</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_LINK">AT91C_EMAC_LINK</a></font></td><td><b></b><br>Set when LINK pin changes value. Optional.</td></tr>