at91sam9260_emac.html

ATMEL AT91SAM9260的中段控制程序！

</null></table><br></null><h2>EMAC Register Description</h2>
<null><a name="EMAC_NCR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_NCR  <i>Network Control Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_NCR">AT91C_EMACB_NCR</a></i> 0xFFFC4000</font></null></ul><br>Network Control Register<table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_LB"></a><b>EMAC_LB</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_LB">AT91C_EMAC_LB</a></font></td><td><b>Loopback. Optional. When set, loopback signal is at high level.</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_LLB"></a><b>EMAC_LLB</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_LLB">AT91C_EMAC_LLB</a></font></td><td><b>Loopback local. </b><br>When set, connects ETX[3:0] to ERX[3:0], ETXEN to ERXDV, forces full duplex and drives ERXCK and ETXCK_REFCK with HCLK divided by 4.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">2</td><td align="CENTER"><a name="EMAC_RE"></a><b>EMAC_RE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RE">AT91C_EMAC_RE</a></font></td><td><b>Receive enable. </b><br>When set, enables the Ethernet MAC to receive data.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="EMAC_TE"></a><b>EMAC_TE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TE">AT91C_EMAC_TE</a></font></td><td><b>Transmit enable. </b><br>When set, enables the Ethernet transmitter to send data.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_MPE"></a><b>EMAC_MPE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_MPE">AT91C_EMAC_MPE</a></font></td><td><b>Management port enable. </b><br>Set to one to enable the management port. When zero, forces MDIO to high impedance state.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_CLRSTAT"></a><b>EMAC_CLRSTAT</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_CLRSTAT">AT91C_EMAC_CLRSTAT</a></font></td><td><b>Clear statistics registers. </b><br>This bit is write-only. Writing a one clears the statistics registers.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_INCSTAT"></a><b>EMAC_INCSTAT</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_INCSTAT">AT91C_EMAC_INCSTAT</a></font></td><td><b>Increment statistics registers. </b><br>This bit is write-only. Writing a one increments all the statistics registers by one for test purposes.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="EMAC_WESTAT"></a><b>EMAC_WESTAT</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_WESTAT">AT91C_EMAC_WESTAT</a></font></td><td><b>Write enable for statistics registers. </b><br>Setting this bit to one makes the statistics registers writable for functional test purposes.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="EMAC_BP"></a><b>EMAC_BP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_BP">AT91C_EMAC_BP</a></font></td><td><b>Back pressure. </b><br>If this field is set, then in half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (default pattern).</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="EMAC_TSTART"></a><b>EMAC_TSTART</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TSTART">AT91C_EMAC_TSTART</a></font></td><td><b>Start Transmission. </b><br>Writing one to this bit starts transmission.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="EMAC_THALT"></a><b>EMAC_THALT</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_THALT">AT91C_EMAC_THALT</a></font></td><td><b>Transmission Halt. </b><br>Writing one to this bit halts transmission as soon as any ongoing frame transmission ends.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="EMAC_TPFR"></a><b>EMAC_TPFR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TPFR">AT91C_EMAC_TPFR</a></font></td><td><b>Transmit pause frame </b><br>Writing one to this bit transmits a pause frame with the pause quantum from the transmit pause quantum register at the next available transmitter idle time.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="EMAC_TZQ"></a><b>EMAC_TZQ</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_TZQ">AT91C_EMAC_TZQ</a></font></td><td><b>Transmit zero quantum pause frame</b><br>Writing a one to this bit transmits a pause frame with zero pause quantum at the next available transmitter idle time.</td></tr>
</null></table>
<a name="EMAC_NCFGR"></a><h4><a href="#EMAC">EMAC</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> EMAC_NCFGR  <i>Network Configuration Register</i></h4><ul><null><font size="-2"><li><b>EMACB</b> <i><a href="AT91SAM9260_h.html#AT91C_EMACB_NCFGR">AT91C_EMACB_NCFGR</a></i> 0xFFFC4004</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="EMAC_SPD"></a><b>EMAC_SPD</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_SPD">AT91C_EMAC_SPD</a></font></td><td><b>Speed. </b><br>Set to 1 to indicate 100 Mbit/sec. operation, 0 for 10 Mbit/sec. Has no other functional effect.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="EMAC_FD"></a><b>EMAC_FD</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_FD">AT91C_EMAC_FD</a></font></td><td><b>Full duplex. </b><br>If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3</td><td align="CENTER"><a name="EMAC_JFRAME"></a><b>EMAC_JFRAME</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_JFRAME">AT91C_EMAC_JFRAME</a></font></td><td><b>Jumbo Frames. </b><br>Not implemented. Set to one to enable jumbo frames of up to 10240 bytes to be accepted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4</td><td align="CENTER"><a name="EMAC_CAF"></a><b>EMAC_CAF</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_CAF">AT91C_EMAC_CAF</a></font></td><td><b>Copy all frames. </b><br>When set to 1, all valid frames are received.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="EMAC_NBC"></a><b>EMAC_NBC</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_NBC">AT91C_EMAC_NBC</a></font></td><td><b>No broadcast. </b><br>When set to 1, frames addressed to the broadcast address of all ones are not received.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="EMAC_MTI"></a><b>EMAC_MTI</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_MTI">AT91C_EMAC_MTI</a></font></td><td><b>Multicast hash event enable</b><br>When set, multicast hash events causes the wol output to be asserted.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="EMAC_UNI"></a><b>EMAC_UNI</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_UNI">AT91C_EMAC_UNI</a></font></td><td><b>Unicast hash enable. </b><br>When set, unicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="EMAC_BIG"></a><b>EMAC_BIG</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_BIG">AT91C_EMAC_BIG</a></font></td><td><b>Receive 1522 bytes. </b><br>When set, the MAC receives up to 1522 bytes. Normally the MAC receives frames up to 1518 bytes in length.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="EMAC_EAE"></a><b>EMAC_EAE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_EAE">AT91C_EMAC_EAE</a></font></td><td><b>External address match enable. </b><br>Optional.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..10</td><td align="CENTER"><a name="EMAC_CLK"></a><b>EMAC_CLK</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_CLK">AT91C_EMAC_CLK</a></font></td><td><b></b><br>The system clock (HCLK) is divided down to generate MDC (the clock for the MDIO). To conform with IEEE standard 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that HCLK is divided by 32.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="EMAC_CLK_HCLK_8"></a><b>EMAC_CLK_HCLK_8</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_CLK_HCLK_8">AT91C_EMAC_CLK_HCLK_8</a></font></td><td><br>HCLK divided by 8</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="EMAC_CLK_HCLK_16"></a><b>EMAC_CLK_HCLK_16</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_CLK_HCLK_16">AT91C_EMAC_CLK_HCLK_16</a></font></td><td><br>HCLK divided by 16</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="EMAC_CLK_HCLK_32"></a><b>EMAC_CLK_HCLK_32</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_CLK_HCLK_32">AT91C_EMAC_CLK_HCLK_32</a></font></td><td><br>HCLK divided by 32</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="EMAC_CLK_HCLK_64"></a><b>EMAC_CLK_HCLK_64</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_CLK_HCLK_64">AT91C_EMAC_CLK_HCLK_64</a></font></td><td><br>HCLK divided by 64</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="EMAC_RTY"></a><b>EMAC_RTY</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RTY">AT91C_EMAC_RTY</a></font></td><td><b></b><br>Retry test. When set, the time between frames is always one time slot. For test purposes only. Must be cleared for normal operation.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13</td><td align="CENTER"><a name="EMAC_PAE"></a><b>EMAC_PAE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_PAE">AT91C_EMAC_PAE</a></font></td><td><b></b><br>Pause Enable. When set, transmission pauses when a valid pause frame is received.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="EMAC_RBOF"></a><b>EMAC_RBOF</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RBOF">AT91C_EMAC_RBOF</a></font></td><td><b></b><br>The system clock (HCLK) is divided down to generate MDC (the clock for the MDIO). To conform with IEEE standard 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that HCLK is divided by 32.<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="EMAC_RBOF_OFFSET_0"></a><b>EMAC_RBOF_OFFSET_0</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RBOF_OFFSET_0">AT91C_EMAC_RBOF_OFFSET_0</a></font></td><td><br>no offset from start of receive buffer</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="EMAC_RBOF_OFFSET_1"></a><b>EMAC_RBOF_OFFSET_1</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RBOF_OFFSET_1">AT91C_EMAC_RBOF_OFFSET_1</a></font></td><td><br>one byte offset from start of receive buffer</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="EMAC_RBOF_OFFSET_2"></a><b>EMAC_RBOF_OFFSET_2</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RBOF_OFFSET_2">AT91C_EMAC_RBOF_OFFSET_2</a></font></td><td><br>two bytes offset from start of receive buffer</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="EMAC_RBOF_OFFSET_3"></a><b>EMAC_RBOF_OFFSET_3</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RBOF_OFFSET_3">AT91C_EMAC_RBOF_OFFSET_3</a></font></td><td><br>three bytes offset from start of receive buffer</td></tr>
</null></table></font>
</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="EMAC_RLCE"></a><b>EMAC_RLCE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_RLCE">AT91C_EMAC_RLCE</a></font></td><td><b>Receive Length field Checking Enable</b><br>When set, frames with measured lengths shorter than their length fields are discarded.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="EMAC_DRFCS"></a><b>EMAC_DRFCS</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_DRFCS">AT91C_EMAC_DRFCS</a></font></td><td><b>Discard Receive FCS</b><br>When set, the FCS field of received frames are not be copied to memory.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="EMAC_EFRHD"></a><b>EMAC_EFRHD</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_EMAC_EFRHD">AT91C_EMAC_EFRHD</a></font></td><td><b></b><br>Enable frames to be received in half-duplex mode while transmitting.</td></tr>