at91sam9260_sdramc.h

ATMEL AT91SAM9260的中段控制程序！

#define 	AT91C_SDRAMC_TRC_2                    (0x2 << 12) /**< (SDRAMC) Value :  2 */
#define 	AT91C_SDRAMC_TRC_3                    (0x3 << 12) /**< (SDRAMC) Value :  3 */
#define 	AT91C_SDRAMC_TRC_4                    (0x4 << 12) /**< (SDRAMC) Value :  4 */
#define 	AT91C_SDRAMC_TRC_5                    (0x5 << 12) /**< (SDRAMC) Value :  5 */
#define 	AT91C_SDRAMC_TRC_6                    (0x6 << 12) /**< (SDRAMC) Value :  6 */
#define 	AT91C_SDRAMC_TRC_7                    (0x7 << 12) /**< (SDRAMC) Value :  7 */
#define 	AT91C_SDRAMC_TRC_8                    (0x8 << 12) /**< (SDRAMC) Value :  8 */
#define 	AT91C_SDRAMC_TRC_9                    (0x9 << 12) /**< (SDRAMC) Value :  9 */
#define 	AT91C_SDRAMC_TRC_10                   (0xA << 12) /**< (SDRAMC) Value : 10 */
#define 	AT91C_SDRAMC_TRC_11                   (0xB << 12) /**< (SDRAMC) Value : 11 */
#define 	AT91C_SDRAMC_TRC_12                   (0xC << 12) /**< (SDRAMC) Value : 12 */
#define 	AT91C_SDRAMC_TRC_13                   (0xD << 12) /**< (SDRAMC) Value : 13 */
#define 	AT91C_SDRAMC_TRC_14                   (0xE << 12) /**< (SDRAMC) Value : 14 */
#define 	AT91C_SDRAMC_TRC_15                   (0xF << 12) /**< (SDRAMC) Value : 15 */
#define AT91C_SDRAMC_TRP      (0xF << 16) /**< (SDRAMC) Number of RAS Precharge Time Cycles */
#define 	AT91C_SDRAMC_TRP_0                    (0x0 << 16) /**< (SDRAMC) Value :  0 */
#define 	AT91C_SDRAMC_TRP_1                    (0x1 << 16) /**< (SDRAMC) Value :  1 */
#define 	AT91C_SDRAMC_TRP_2                    (0x2 << 16) /**< (SDRAMC) Value :  2 */
#define 	AT91C_SDRAMC_TRP_3                    (0x3 << 16) /**< (SDRAMC) Value :  3 */
#define 	AT91C_SDRAMC_TRP_4                    (0x4 << 16) /**< (SDRAMC) Value :  4 */
#define 	AT91C_SDRAMC_TRP_5                    (0x5 << 16) /**< (SDRAMC) Value :  5 */
#define 	AT91C_SDRAMC_TRP_6                    (0x6 << 16) /**< (SDRAMC) Value :  6 */
#define 	AT91C_SDRAMC_TRP_7                    (0x7 << 16) /**< (SDRAMC) Value :  7 */
#define 	AT91C_SDRAMC_TRP_8                    (0x8 << 16) /**< (SDRAMC) Value :  8 */
#define 	AT91C_SDRAMC_TRP_9                    (0x9 << 16) /**< (SDRAMC) Value :  9 */
#define 	AT91C_SDRAMC_TRP_10                   (0xA << 16) /**< (SDRAMC) Value : 10 */
#define 	AT91C_SDRAMC_TRP_11                   (0xB << 16) /**< (SDRAMC) Value : 11 */
#define 	AT91C_SDRAMC_TRP_12                   (0xC << 16) /**< (SDRAMC) Value : 12 */
#define 	AT91C_SDRAMC_TRP_13                   (0xD << 16) /**< (SDRAMC) Value : 13 */
#define 	AT91C_SDRAMC_TRP_14                   (0xE << 16) /**< (SDRAMC) Value : 14 */
#define 	AT91C_SDRAMC_TRP_15                   (0xF << 16) /**< (SDRAMC) Value : 15 */
#define AT91C_SDRAMC_TRCD     (0xF << 20) /**< (SDRAMC) Number of RAS to CAS Delay Cycles */
#define 	AT91C_SDRAMC_TRCD_0                    (0x0 << 20) /**< (SDRAMC) Value :  0 */
#define 	AT91C_SDRAMC_TRCD_1                    (0x1 << 20) /**< (SDRAMC) Value :  1 */
#define 	AT91C_SDRAMC_TRCD_2                    (0x2 << 20) /**< (SDRAMC) Value :  2 */
#define 	AT91C_SDRAMC_TRCD_3                    (0x3 << 20) /**< (SDRAMC) Value :  3 */
#define 	AT91C_SDRAMC_TRCD_4                    (0x4 << 20) /**< (SDRAMC) Value :  4 */
#define 	AT91C_SDRAMC_TRCD_5                    (0x5 << 20) /**< (SDRAMC) Value :  5 */
#define 	AT91C_SDRAMC_TRCD_6                    (0x6 << 20) /**< (SDRAMC) Value :  6 */
#define 	AT91C_SDRAMC_TRCD_7                    (0x7 << 20) /**< (SDRAMC) Value :  7 */
#define 	AT91C_SDRAMC_TRCD_8                    (0x8 << 20) /**< (SDRAMC) Value :  8 */
#define 	AT91C_SDRAMC_TRCD_9                    (0x9 << 20) /**< (SDRAMC) Value :  9 */
#define 	AT91C_SDRAMC_TRCD_10                   (0xA << 20) /**< (SDRAMC) Value : 10 */
#define 	AT91C_SDRAMC_TRCD_11                   (0xB << 20) /**< (SDRAMC) Value : 11 */
#define 	AT91C_SDRAMC_TRCD_12                   (0xC << 20) /**< (SDRAMC) Value : 12 */
#define 	AT91C_SDRAMC_TRCD_13                   (0xD << 20) /**< (SDRAMC) Value : 13 */
#define 	AT91C_SDRAMC_TRCD_14                   (0xE << 20) /**< (SDRAMC) Value : 14 */
#define 	AT91C_SDRAMC_TRCD_15                   (0xF << 20) /**< (SDRAMC) Value : 15 */
#define AT91C_SDRAMC_TRAS     (0xF << 24) /**< (SDRAMC) Number of RAS Active Time Cycles */
#define 	AT91C_SDRAMC_TRAS_0                    (0x0 << 24) /**< (SDRAMC) Value :  0 */
#define 	AT91C_SDRAMC_TRAS_1                    (0x1 << 24) /**< (SDRAMC) Value :  1 */
#define 	AT91C_SDRAMC_TRAS_2                    (0x2 << 24) /**< (SDRAMC) Value :  2 */
#define 	AT91C_SDRAMC_TRAS_3                    (0x3 << 24) /**< (SDRAMC) Value :  3 */
#define 	AT91C_SDRAMC_TRAS_4                    (0x4 << 24) /**< (SDRAMC) Value :  4 */
#define 	AT91C_SDRAMC_TRAS_5                    (0x5 << 24) /**< (SDRAMC) Value :  5 */
#define 	AT91C_SDRAMC_TRAS_6                    (0x6 << 24) /**< (SDRAMC) Value :  6 */
#define 	AT91C_SDRAMC_TRAS_7                    (0x7 << 24) /**< (SDRAMC) Value :  7 */
#define 	AT91C_SDRAMC_TRAS_8                    (0x8 << 24) /**< (SDRAMC) Value :  8 */
#define 	AT91C_SDRAMC_TRAS_9                    (0x9 << 24) /**< (SDRAMC) Value :  9 */
#define 	AT91C_SDRAMC_TRAS_10                   (0xA << 24) /**< (SDRAMC) Value : 10 */
#define 	AT91C_SDRAMC_TRAS_11                   (0xB << 24) /**< (SDRAMC) Value : 11 */
#define 	AT91C_SDRAMC_TRAS_12                   (0xC << 24) /**< (SDRAMC) Value : 12 */
#define 	AT91C_SDRAMC_TRAS_13                   (0xD << 24) /**< (SDRAMC) Value : 13 */
#define 	AT91C_SDRAMC_TRAS_14                   (0xE << 24) /**< (SDRAMC) Value : 14 */
#define 	AT91C_SDRAMC_TRAS_15                   (0xF << 24) /**< (SDRAMC) Value : 15 */
#define AT91C_SDRAMC_TXSR     (0xF << 28) /**< (SDRAMC) Number of Command Recovery Time Cycles */
#define 	AT91C_SDRAMC_TXSR_0                    (0x0 << 28) /**< (SDRAMC) Value :  0 */
#define 	AT91C_SDRAMC_TXSR_1                    (0x1 << 28) /**< (SDRAMC) Value :  1 */
#define 	AT91C_SDRAMC_TXSR_2                    (0x2 << 28) /**< (SDRAMC) Value :  2 */
#define 	AT91C_SDRAMC_TXSR_3                    (0x3 << 28) /**< (SDRAMC) Value :  3 */
#define 	AT91C_SDRAMC_TXSR_4                    (0x4 << 28) /**< (SDRAMC) Value :  4 */
#define 	AT91C_SDRAMC_TXSR_5                    (0x5 << 28) /**< (SDRAMC) Value :  5 */
#define 	AT91C_SDRAMC_TXSR_6                    (0x6 << 28) /**< (SDRAMC) Value :  6 */
#define 	AT91C_SDRAMC_TXSR_7                    (0x7 << 28) /**< (SDRAMC) Value :  7 */
#define 	AT91C_SDRAMC_TXSR_8                    (0x8 << 28) /**< (SDRAMC) Value :  8 */
#define 	AT91C_SDRAMC_TXSR_9                    (0x9 << 28) /**< (SDRAMC) Value :  9 */
#define 	AT91C_SDRAMC_TXSR_10                   (0xA << 28) /**< (SDRAMC) Value : 10 */
#define 	AT91C_SDRAMC_TXSR_11                   (0xB << 28) /**< (SDRAMC) Value : 11 */
#define 	AT91C_SDRAMC_TXSR_12                   (0xC << 28) /**< (SDRAMC) Value : 12 */
#define 	AT91C_SDRAMC_TXSR_13                   (0xD << 28) /**< (SDRAMC) Value : 13 */
#define 	AT91C_SDRAMC_TXSR_14                   (0xE << 28) /**< (SDRAMC) Value : 14 */
#define 	AT91C_SDRAMC_TXSR_15                   (0xF << 28) /**< (SDRAMC) Value : 15 */
/* --- Register SDRAMC_HSR */
#define AT91C_SDRAMC_DA       (0x1 << 0 ) /**< (SDRAMC) Decode Cycle Enable Bit */
#define 	AT91C_SDRAMC_DA_DISABLE              0x0 /**< (SDRAMC) Disable Decode Cycle */
#define 	AT91C_SDRAMC_DA_ENABLE               0x1 /**< (SDRAMC) Enable Decode Cycle */
/* --- Register SDRAMC_LPR */
#define AT91C_SDRAMC_LPCB     (0x3 << 0 ) /**< (SDRAMC) Low-power Configurations */
#define 	AT91C_SDRAMC_LPCB_DISABLE              0x0 /**< (SDRAMC) Disable Low Power Features */
#define 	AT91C_SDRAMC_LPCB_SELF_REFRESH         0x1 /**< (SDRAMC) Enable SELF_REFRESH */
#define 	AT91C_SDRAMC_LPCB_POWER_DOWN           0x2 /**< (SDRAMC) Enable POWER_DOWN */
#define 	AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN      0x3 /**< (SDRAMC) Enable DEEP_POWER_DOWN */
#define AT91C_SDRAMC_PASR     (0x7 << 4 ) /**< (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM) */
#define AT91C_SDRAMC_TCSR     (0x3 << 8 ) /**< (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM) */
#define AT91C_SDRAMC_DS       (0x3 << 10) /**< (SDRAMC) Drive Strenght (only for Low Power SDRAM) */
#define AT91C_SDRAMC_TIMEOUT  (0x3 << 12) /**< (SDRAMC) Time to define when Low Power Mode is enabled */
#define 	AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES         (0x0 << 12) /**< (SDRAMC) Activate SDRAM Low Power Mode Immediately */
#define 	AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES        (0x1 << 12) /**< (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer */
#define 	AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES       (0x2 << 12) /**< (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer */
/* --- Register SDRAMC_IER */
#define AT91C_SDRAMC_RES      (0x1 << 0 ) /**< (SDRAMC) Refresh Error Status */
/* --- Register SDRAMC_IDR */
#define AT91C_SDRAMC_RES      (0x1 << 0 ) /**< (SDRAMC) Refresh Error Status */
/* --- Register SDRAMC_IMR */
#define AT91C_SDRAMC_RES      (0x1 << 0 ) /**< (SDRAMC) Refresh Error Status */
/* --- Register SDRAMC_ISR */
#define AT91C_SDRAMC_RES      (0x1 << 0 ) /**< (SDRAMC) Refresh Error Status */
/* --- Register SDRAMC_MDR */
#define AT91C_SDRAMC_MD       (0x3 << 0 ) /**< (SDRAMC) Memory Device Type */
#define 	AT91C_SDRAMC_MD_SDRAM                0x0 /**< (SDRAMC) SDRAM Mode */
#define 	AT91C_SDRAMC_MD_LOW_POWER_SDRAM      0x1 /**< (SDRAMC) SDRAM Low Power Mode */

#endif /* __AT91SAM9260_SDRAMC_H */