📄 at91sam9260_smc.h
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#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS (0x3 << 28) /**< (SMC) Page Size */
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) /**< (SMC) 4 bytes. */
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) /**< (SMC) 8 bytes. */
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) /**< (SMC) 16 bytes. */
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) /**< (SMC) External NWAIT disabled. */
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW (0x3 << 12) /**< (SMC) Data Bus Width */
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) /**< (SMC) 8 bits. */
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) /**< (SMC) 16 bits. */
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS (0x3 << 28) /**< (SMC) Page Size */
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) /**< (SMC) 4 bytes. */
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) /**< (SMC) 8 bytes. */
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) /**< (SMC) 16 bytes. */
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) /**< (SMC) External NWAIT disabled. */
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW (0x3 << 12) /**< (SMC) Data Bus Width */
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) /**< (SMC) 8 bits. */
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) /**< (SMC) 16 bits. */
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS (0x3 << 28) /**< (SMC) Page Size */
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) /**< (SMC) 4 bytes. */
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) /**< (SMC) 8 bytes. */
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) /**< (SMC) 16 bytes. */
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) /**< (SMC) External NWAIT disabled. */
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW (0x3 << 12) /**< (SMC) Data Bus Width */
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) /**< (SMC) 8 bits. */
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) /**< (SMC) 16 bits. */
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS (0x3 << 28) /**< (SMC) Page Size */
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) /**< (SMC) 4 bytes. */
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) /**< (SMC) 8 bytes. */
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) /**< (SMC) 16 bytes. */
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) /**< (SMC) External NWAIT disabled. */
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW (0x3 << 12) /**< (SMC) Data Bus Width */
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) /**< (SMC) 8 bits. */
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) /**< (SMC) 16 bits. */
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS (0x3 << 28) /**< (SMC) Page Size */
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) /**< (SMC) 4 bytes. */
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) /**< (SMC) 8 bytes. */
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) /**< (SMC) 16 bytes. */
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
/* --- Register SMC_SETUP */
#define AT91C_SMC_NWESETUP (0x3F << 0 ) /**< (SMC) NWE Setup Length */
#define AT91C_SMC_NCSSETUPWR (0x3F << 8 ) /**< (SMC) NCS Setup Length in WRite Access */
#define AT91C_SMC_NRDSETUP (0x3F << 16) /**< (SMC) NRD Setup Length */
#define AT91C_SMC_NCSSETUPRD (0x3F << 24) /**< (SMC) NCS Setup Length in ReaD Access */
/* --- Register SMC_PULSE */
#define AT91C_SMC_NWEPULSE (0x7F << 0 ) /**< (SMC) NWE Pulse Length */
#define AT91C_SMC_NCSPULSEWR (0x7F << 8 ) /**< (SMC) NCS Pulse Length in WRite Access */
#define AT91C_SMC_NRDPULSE (0x7F << 16) /**< (SMC) NRD Pulse Length */
#define AT91C_SMC_NCSPULSERD (0x7F << 24) /**< (SMC) NCS Pulse Length in ReaD Access */
/* --- Register SMC_CYC */
#define AT91C_SMC_NWECYCLE (0x1FF << 0 ) /**< (SMC) Total Write Cycle Length */
#define AT91C_SMC_NRDCYCLE (0x1FF << 16) /**< (SMC) Total Read Cycle Length */
/* --- Register SMC_CTRL */
#define AT91C_SMC_READMODE (0x1 << 0 ) /**< (SMC) Read Mode */
#define AT91C_SMC_WRITEMODE (0x1 << 1 ) /**< (SMC) Write Mode */
#define AT91C_SMC_NWAITM (0x3 << 5 ) /**< (SMC) NWAIT Mode */
#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) /**< (SMC) External NWAIT disabled. */
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) /**< (SMC) External NWAIT enabled in frozen mode. */
#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) /**< (SMC) External NWAIT enabled in ready mode. */
#define AT91C_SMC_BAT (0x1 << 8 ) /**< (SMC) Byte Access Type */
#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) /**< (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3. */
#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) /**< (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd. */
#define AT91C_SMC_DBW (0x3 << 12) /**< (SMC) Data Bus Width */
#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) /**< (SMC) 8 bits. */
#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) /**< (SMC) 16 bits. */
#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) /**< (SMC) 32 bits. */
#define AT91C_SMC_TDF (0xF << 16) /**< (SMC) Data Float Time. */
#define AT91C_SMC_TDFEN (0x1 << 20) /**< (SMC) TDF Enabled. */
#define AT91C_SMC_PMEN (0x1 << 24) /**< (SMC) Page Mode Enabled. */
#define AT91C_SMC_PS (0x3 << 28) /**< (SMC) Page Size */
#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) /**< (SMC) 4 bytes. */
#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) /**< (SMC) 8 bytes. */
#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) /**< (SMC) 16 bytes. */
#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) /**< (SMC) 32 bytes. */
#endif /* __AT91SAM9260_SMC_H */
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