at91sam9260_usart.h

ATMEL AT91SAM9260的中段控制程序！

/* linux/include/asm-arm/arch-at91sam9260/at91sam9260_usart.h
 * 
 * Hardware definition for the usart peripheral in the ATMEL at91sam9260 processor
 * 
 * Generated  01/16/2006 (17:06:46) AT91 SW Application Group from  V
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91SAM9260_USART_H
#define __AT91SAM9260_USART_H

/* -------------------------------------------------------- */
/* USART ID definitions for  AT91SAM9260           */
/* -------------------------------------------------------- */
#ifndef AT91C_ID_US0
#define AT91C_ID_US0   	 6 /**< USART 0 id */
#endif /* AT91C_ID_US0 */
#ifndef AT91C_ID_US1
#define AT91C_ID_US1   	 7 /**< USART 1 id */
#endif /* AT91C_ID_US1 */
#ifndef AT91C_ID_US2
#define AT91C_ID_US2   	 8 /**< USART 2 id */
#endif /* AT91C_ID_US2 */
#ifndef AT91C_ID_US3
#define AT91C_ID_US3   	23 /**< USART 3 id */
#endif /* AT91C_ID_US3 */
#ifndef AT91C_ID_US4
#define AT91C_ID_US4   	24 /**< USART 4 id */
#endif /* AT91C_ID_US4 */
#ifndef AT91C_ID_US5
#define AT91C_ID_US5   	25 /**< USART 5 id */
#endif /* AT91C_ID_US5 */

/* -------------------------------------------------------- */
/* USART Base Address definitions for  AT91SAM9260   */
/* -------------------------------------------------------- */
#define AT91C_BASE_US0       	0xFFFB0000 /**< US0 base address */
#define AT91C_BASE_US1       	0xFFFB4000 /**< US1 base address */
#define AT91C_BASE_US2       	0xFFFB8000 /**< US2 base address */
#define AT91C_BASE_US3       	0xFFFD0000 /**< US3 base address */
#define AT91C_BASE_US4       	0xFFFD4000 /**< US4 base address */
#define AT91C_BASE_US5       	0xFFFD8000 /**< US5 base address */

/* -------------------------------------------------------- */
/* PIO definition for USART hardware peripheral */
/* -------------------------------------------------------- */
#define AT91C_PB27_CTS0     	(1 << 27) /**< USART 0 Clear To Send */
#define AT91C_PB23_DCD0     	(1 << 23) /**< USART 0 Data Carrier Detect */
#define AT91C_PB22_DSR0     	(1 << 22) /**< USART 0 Data Set ready */
#define AT91C_PB24_DTR0     	(1 << 24) /**< USART 0 Data Terminal ready */
#define AT91C_PB25_RI0      	(1 << 25) /**< USART 0 Ring Indicator */
#define AT91C_PB26_RTS0     	(1 << 26) /**< USART 0 Ready To Send */
#define AT91C_PB5_RXD0     	(1 << 5) /**< USART 0 Receive Data */
#define AT91C_PA31_SCK0     	(1 << 31) /**< USART 0 Serial Clock */
#define AT91C_PB4_TXD0     	(1 << 4) /**< USART 0 Transmit Data */

#define AT91C_PB29_CTS1     	(1 << 29) /**< USART 1 Clear To Send */
#define AT91C_PB28_RTS1     	(1 << 28) /**< USART 1 Ready To Send */
#define AT91C_PB7_RXD1     	(1 << 7) /**< USART 1 Receive Data */
#define AT91C_PA29_SCK1     	(1 << 29) /**< USART 1 Serial Clock */
#define AT91C_PB6_TXD1     	(1 << 6) /**< USART 1 Transmit Data */

#define AT91C_PA5_CTS2     	(1 << 5) /**< USART 2 Clear To Send */
#define AT91C_PA4_RTS2     	(1 << 4) /**< USART 2 Ready To Send */
#define AT91C_PB9_RXD2     	(1 << 9) /**< USART 2 Receive Data */
#define AT91C_PA30_SCK2     	(1 << 30) /**< USART 2 Serial Clock */
#define AT91C_PB8_TXD2     	(1 << 8) /**< USART 2 Transmit Data */

#define AT91C_PC10_CTS3     	(1 << 10) /**< USART 3 Clear To Send */
#define AT91C_PC8_RTS3     	(1 << 8) /**< USART 3 Ready To Send */
#define AT91C_PB11_RXD3     	(1 << 11) /**< USART 3 Receive Data */
#define AT91C_PC0_SCK3     	(1 << 0) /**< USART 3 Serial Clock */
#define AT91C_PB10_TXD3     	(1 << 10) /**< USART 3 Transmit Data */

#define AT91C_PA30_RXD4     	(1 << 30) /**< USART 4 Receive Data */
#define AT91C_PA31_TXD4     	(1 << 31) /**< USART 4 Transmit Data */

#define AT91C_PB13_RXD5     	(1 << 13) /**< USART 5 Receive Data */
#define AT91C_PB12_TXD5     	(1 << 12) /**< USART 5 Transmit Data */


/* -------------------------------------------------------- */
/* Register offset definition for USART hardware peripheral */
/* -------------------------------------------------------- */
#define US_CR 	(0x0000) 	/**< Control Register */
#define US_MR 	(0x0004) 	/**< Mode Register */
#define US_IER 	(0x0008) 	/**< Interrupt Enable Register */
#define US_IDR 	(0x000C) 	/**< Interrupt Disable Register */
#define US_IMR 	(0x0010) 	/**< Interrupt Mask Register */
#define US_CSR 	(0x0014) 	/**< Channel Status Register */
#define US_RHR 	(0x0018) 	/**< Receiver Holding Register */
#define US_THR 	(0x001C) 	/**< Transmitter Holding Register */
#define US_BRGR 	(0x0020) 	/**< Baud Rate Generator Register */
#define US_RTOR 	(0x0024) 	/**< Receiver Time-out Register */
#define US_TTGR 	(0x0028) 	/**< Transmitter Time-guard Register */
#define US_FIDI 	(0x0040) 	/**< FI_DI_Ratio Register */
#define US_NER 	(0x0044) 	/**< Nb Errors Register */
#define US_IF 	(0x004C) 	/**< IRDA_FILTER Register */
#define US_RPR 	(0x0100) 	/**< Receive Pointer Register */
#define US_RCR 	(0x0104) 	/**< Receive Counter Register */
#define US_TPR 	(0x0108) 	/**< Transmit Pointer Register */
#define US_TCR 	(0x010C) 	/**< Transmit Counter Register */
#define US_RNPR 	(0x0110) 	/**< Receive Next Pointer Register */
#define US_RNCR 	(0x0114) 	/**< Receive Next Counter Register */
#define US_TNPR 	(0x0118) 	/**< Transmit Next Pointer Register */
#define US_TNCR 	(0x011C) 	/**< Transmit Next Counter Register */
#define US_PTCR 	(0x0120) 	/**< PDC Transfer Control Register */
#define US_PTSR 	(0x0124) 	/**< PDC Transfer Status Register */

/* -------------------------------------------------------- */
/* Bitfields definition for USART hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register US_CR */
#define AT91C_US_RSTRX        (0x1 << 2 ) /**< (USART) Reset Receiver */
#define AT91C_US_RSTTX        (0x1 << 3 ) /**< (USART) Reset Transmitter */
#define AT91C_US_RXEN         (0x1 << 4 ) /**< (USART) Receiver Enable */
#define AT91C_US_RXDIS        (0x1 << 5 ) /**< (USART) Receiver Disable */
#define AT91C_US_TXEN         (0x1 << 6 ) /**< (USART) Transmitter Enable */
#define AT91C_US_TXDIS        (0x1 << 7 ) /**< (USART) Transmitter Disable */
#define AT91C_US_RSTSTA       (0x1 << 8 ) /**< (USART) Reset Status Bits */