at91sam9260_sys.h

ATMEL AT91SAM9260的中段控制程序！

#define DBGU_TPR 	(0x0908) 	/**< Transmit Pointer Register */
#define DBGU_TCR 	(0x090C) 	/**< Transmit Counter Register */
#define DBGU_RNPR 	(0x0910) 	/**< Receive Next Pointer Register */
#define DBGU_RNCR 	(0x0914) 	/**< Receive Next Counter Register */
#define DBGU_TNPR 	(0x0918) 	/**< Transmit Next Pointer Register */
#define DBGU_TNCR 	(0x091C) 	/**< Transmit Next Counter Register */
#define DBGU_PTCR 	(0x0920) 	/**< PDC Transfer Control Register */
#define DBGU_PTSR 	(0x0924) 	/**< PDC Transfer Status Register */
#define PIOA_PER 	(0x0A00) 	/**< PIO Enable Register */
#define PIOA_PDR 	(0x0A04) 	/**< PIO Disable Register */
#define PIOA_PSR 	(0x0A08) 	/**< PIO Status Register */
#define PIOA_OER 	(0x0A10) 	/**< Output Enable Register */
#define PIOA_ODR 	(0x0A14) 	/**< Output Disable Registerr */
#define PIOA_OSR 	(0x0A18) 	/**< Output Status Register */
#define PIOA_IFER 	(0x0A20) 	/**< Input Filter Enable Register */
#define PIOA_IFDR 	(0x0A24) 	/**< Input Filter Disable Register */
#define PIOA_IFSR 	(0x0A28) 	/**< Input Filter Status Register */
#define PIOA_SODR 	(0x0A30) 	/**< Set Output Data Register */
#define PIOA_CODR 	(0x0A34) 	/**< Clear Output Data Register */
#define PIOA_ODSR 	(0x0A38) 	/**< Output Data Status Register */
#define PIOA_PDSR 	(0x0A3C) 	/**< Pin Data Status Register */
#define PIOA_IER 	(0x0A40) 	/**< Interrupt Enable Register */
#define PIOA_IDR 	(0x0A44) 	/**< Interrupt Disable Register */
#define PIOA_IMR 	(0x0A48) 	/**< Interrupt Mask Register */
#define PIOA_ISR 	(0x0A4C) 	/**< Interrupt Status Register */
#define PIOA_MDER 	(0x0A50) 	/**< Multi-driver Enable Register */
#define PIOA_MDDR 	(0x0A54) 	/**< Multi-driver Disable Register */
#define PIOA_MDSR 	(0x0A58) 	/**< Multi-driver Status Register */
#define PIOA_PPUDR 	(0x0A60) 	/**< Pull-up Disable Register */
#define PIOA_PPUER 	(0x0A64) 	/**< Pull-up Enable Register */
#define PIOA_PPUSR 	(0x0A68) 	/**< Pull-up Status Register */
#define PIOA_ASR 	(0x0A70) 	/**< Select A Register */
#define PIOA_BSR 	(0x0A74) 	/**< Select B Register */
#define PIOA_ABSR 	(0x0A78) 	/**< AB Select Status Register */
#define PIOA_OWER 	(0x0AA0) 	/**< Output Write Enable Register */
#define PIOA_OWDR 	(0x0AA4) 	/**< Output Write Disable Register */
#define PIOA_OWSR 	(0x0AA8) 	/**< Output Write Status Register */
#define PIOB_PER 	(0x0C00) 	/**< PIO Enable Register */
#define PIOB_PDR 	(0x0C04) 	/**< PIO Disable Register */
#define PIOB_PSR 	(0x0C08) 	/**< PIO Status Register */
#define PIOB_OER 	(0x0C10) 	/**< Output Enable Register */
#define PIOB_ODR 	(0x0C14) 	/**< Output Disable Registerr */
#define PIOB_OSR 	(0x0C18) 	/**< Output Status Register */
#define PIOB_IFER 	(0x0C20) 	/**< Input Filter Enable Register */
#define PIOB_IFDR 	(0x0C24) 	/**< Input Filter Disable Register */
#define PIOB_IFSR 	(0x0C28) 	/**< Input Filter Status Register */
#define PIOB_SODR 	(0x0C30) 	/**< Set Output Data Register */
#define PIOB_CODR 	(0x0C34) 	/**< Clear Output Data Register */
#define PIOB_ODSR 	(0x0C38) 	/**< Output Data Status Register */
#define PIOB_PDSR 	(0x0C3C) 	/**< Pin Data Status Register */
#define PIOB_IER 	(0x0C40) 	/**< Interrupt Enable Register */
#define PIOB_IDR 	(0x0C44) 	/**< Interrupt Disable Register */
#define PIOB_IMR 	(0x0C48) 	/**< Interrupt Mask Register */
#define PIOB_ISR 	(0x0C4C) 	/**< Interrupt Status Register */
#define PIOB_MDER 	(0x0C50) 	/**< Multi-driver Enable Register */
#define PIOB_MDDR 	(0x0C54) 	/**< Multi-driver Disable Register */
#define PIOB_MDSR 	(0x0C58) 	/**< Multi-driver Status Register */
#define PIOB_PPUDR 	(0x0C60) 	/**< Pull-up Disable Register */
#define PIOB_PPUER 	(0x0C64) 	/**< Pull-up Enable Register */
#define PIOB_PPUSR 	(0x0C68) 	/**< Pull-up Status Register */
#define PIOB_ASR 	(0x0C70) 	/**< Select A Register */
#define PIOB_BSR 	(0x0C74) 	/**< Select B Register */
#define PIOB_ABSR 	(0x0C78) 	/**< AB Select Status Register */
#define PIOB_OWER 	(0x0CA0) 	/**< Output Write Enable Register */
#define PIOB_OWDR 	(0x0CA4) 	/**< Output Write Disable Register */
#define PIOB_OWSR 	(0x0CA8) 	/**< Output Write Status Register */
#define PIOC_PER 	(0x0E00) 	/**< PIO Enable Register */
#define PIOC_PDR 	(0x0E04) 	/**< PIO Disable Register */
#define PIOC_PSR 	(0x0E08) 	/**< PIO Status Register */
#define PIOC_OER 	(0x0E10) 	/**< Output Enable Register */
#define PIOC_ODR 	(0x0E14) 	/**< Output Disable Registerr */
#define PIOC_OSR 	(0x0E18) 	/**< Output Status Register */
#define PIOC_IFER 	(0x0E20) 	/**< Input Filter Enable Register */
#define PIOC_IFDR 	(0x0E24) 	/**< Input Filter Disable Register */
#define PIOC_IFSR 	(0x0E28) 	/**< Input Filter Status Register */
#define PIOC_SODR 	(0x0E30) 	/**< Set Output Data Register */
#define PIOC_CODR 	(0x0E34) 	/**< Clear Output Data Register */
#define PIOC_ODSR 	(0x0E38) 	/**< Output Data Status Register */
#define PIOC_PDSR 	(0x0E3C) 	/**< Pin Data Status Register */
#define PIOC_IER 	(0x0E40) 	/**< Interrupt Enable Register */
#define PIOC_IDR 	(0x0E44) 	/**< Interrupt Disable Register */
#define PIOC_IMR 	(0x0E48) 	/**< Interrupt Mask Register */
#define PIOC_ISR 	(0x0E4C) 	/**< Interrupt Status Register */
#define PIOC_MDER 	(0x0E50) 	/**< Multi-driver Enable Register */
#define PIOC_MDDR 	(0x0E54) 	/**< Multi-driver Disable Register */
#define PIOC_MDSR 	(0x0E58) 	/**< Multi-driver Status Register */
#define PIOC_PPUDR 	(0x0E60) 	/**< Pull-up Disable Register */
#define PIOC_PPUER 	(0x0E64) 	/**< Pull-up Enable Register */
#define PIOC_PPUSR 	(0x0E68) 	/**< Pull-up Status Register */
#define PIOC_ASR 	(0x0E70) 	/**< Select A Register */
#define PIOC_BSR 	(0x0E74) 	/**< Select B Register */
#define PIOC_ABSR 	(0x0E78) 	/**< AB Select Status Register */
#define PIOC_OWER 	(0x0EA0) 	/**< Output Write Enable Register */
#define PIOC_OWDR 	(0x0EA4) 	/**< Output Write Disable Register */
#define PIOC_OWSR 	(0x0EA8) 	/**< Output Write Status Register */
#define PMC_SCER 	(0x1200) 	/**< System Clock Enable Register */
#define PMC_SCDR 	(0x1204) 	/**< System Clock Disable Register */
#define PMC_SCSR 	(0x1208) 	/**< System Clock Status Register */
#define PMC_PCER 	(0x1210) 	/**< Peripheral Clock Enable Register */
#define PMC_PCDR 	(0x1214) 	/**< Peripheral Clock Disable Register */
#define PMC_PCSR 	(0x1218) 	/**< Peripheral Clock Status Register */
#define PMC_MOR 	(0x1220) 	/**< Main Oscillator Register */
#define PMC_MCFR 	(0x1224) 	/**< Main Clock  Frequency Register */
#define PMC_PLLAR 	(0x1228) 	/**< PLL A Register */
#define PMC_PLLBR 	(0x122C) 	/**< PLL B Register */
#define PMC_MCKR 	(0x1230) 	/**< Master Clock Register */
#define PMC_PCKR 	(0x1240) 	/**< Programmable Clock Register */
#define PMC_IER 	(0x1260) 	/**< Interrupt Enable Register */
#define PMC_IDR 	(0x1264) 	/**< Interrupt Disable Register */
#define PMC_SR 	(0x1268) 	/**< Status Register */
#define PMC_IMR 	(0x126C) 	/**< Interrupt Mask Register */
#define RSTC_RCR 	(0x1300) 	/**< Reset Control Register */
#define RSTC_RSR 	(0x1304) 	/**< Reset Status Register */
#define RSTC_RMR 	(0x1308) 	/**< Reset Mode Register */
#define SHDWC_SHCR 	(0x1310) 	/**< Shut Down Control Register */
#define SHDWC_SHMR 	(0x1314) 	/**< Shut Down Mode Register */
#define SHDWC_SHSR 	(0x1318) 	/**< Shut Down Status Register */
#define RTTC_RTMR 	(0x1320) 	/**< Real-time Mode Register */
#define RTTC_RTAR 	(0x1324) 	/**< Real-time Alarm Register */
#define RTTC_RTVR 	(0x1328) 	/**< Real-time Value Register */
#define RTTC_RTSR 	(0x132C) 	/**< Real-time Status Register */
#define PITC_PIMR 	(0x1330) 	/**< Period Interval Mode Register */
#define PITC_PISR 	(0x1334) 	/**< Period Interval Status Register */
#define PITC_PIVR 	(0x1338) 	/**< Period Interval Value Register */
#define PITC_PIIR 	(0x133C) 	/**< Period Interval Image Register */
#define WDTC_WDCR 	(0x1340) 	/**< Watchdog Control Register */
#define WDTC_WDMR 	(0x1344) 	/**< Watchdog Mode Register */
#define WDTC_WDSR 	(0x1348) 	/**< Watchdog Status Register */
#define SYS_GPBR0 	(0x1350) 	/**< General Purpose Register 0 */
#define SYS_GPBR1 	(0x1354) 	/**< General Purpose Register 1 */
#define SYS_GPBR2 	(0x1358) 	/**< General Purpose Register 2 */
#define SYS_GPBR3 	(0x135C) 	/**< General Purpose Register 3 */

/* -------------------------------------------------------- */
/* Bitfields definition for SYS hardware peripheral */
/* -------------------------------------------------------- */
/* --- Register GPBR */
/* --- Register GPBR */
/* --- Register GPBR */
/* --- Register GPBR */

#endif /* __AT91SAM9260_SYS_H */