at91sam9260_sys.h

ATMEL AT91SAM9260的中段控制程序！

/* linux/include/asm-arm/arch-at91sam9260/at91sam9260_sys.h
 * 
 * Hardware definition for the sys peripheral in the ATMEL at91sam9260 processor
 * 
 * Generated  01/16/2006 (17:06:46) AT91 SW Application Group from SYS_SAM9260 V1.2
 * 
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 * 
 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * You should have received a copy of the  GNU General Public License along
 * with this program; if not, write  to the Free Software Foundation, Inc.,
 * 675 Mass Ave, Cambridge, MA 02139, USA.
 */


#ifndef __AT91SAM9260_SYS_H
#define __AT91SAM9260_SYS_H

/* -------------------------------------------------------- */
/* SYS ID definitions for  AT91SAM9260           */
/* -------------------------------------------------------- */

/* -------------------------------------------------------- */
/* SYS Base Address definitions for  AT91SAM9260   */
/* -------------------------------------------------------- */
#define AT91C_BASE_SYS       	0xFFFFFD00 /**< SYS base address */

/* -------------------------------------------------------- */
/* PIO definition for SYS hardware peripheral */
/* -------------------------------------------------------- */

/* -------------------------------------------------------- */
/* Register offset definition for SYS hardware peripheral */
/* -------------------------------------------------------- */
#define SDRAMC_MR 	(0x0000) 	/**< SDRAM Controller Mode Register */
#define SDRAMC_TR 	(0x0004) 	/**< SDRAM Controller Refresh Timer Register */
#define SDRAMC_CR 	(0x0008) 	/**< SDRAM Controller Configuration Register */
#define SDRAMC_HSR 	(0x000C) 	/**< SDRAM Controller High Speed Register */
#define SDRAMC_LPR 	(0x0010) 	/**< SDRAM Controller Low Power Register */
#define SDRAMC_IER 	(0x0014) 	/**< SDRAM Controller Interrupt Enable Register */
#define SDRAMC_IDR 	(0x0018) 	/**< SDRAM Controller Interrupt Disable Register */
#define SDRAMC_IMR 	(0x001C) 	/**< SDRAM Controller Interrupt Mask Register */
#define SDRAMC_ISR 	(0x0020) 	/**< SDRAM Controller Interrupt Mask Register */
#define SDRAMC_MDR 	(0x0024) 	/**< SDRAM Memory Device Register */
#define SMC_SETUP0 	(0x0200) 	/**<  Setup Register for CS 0 */
#define SMC_PULSE0 	(0x0204) 	/**<  Pulse Register for CS 0 */
#define SMC_CYCLE0 	(0x0208) 	/**<  Cycle Register for CS 0 */
#define SMC_CTRL0 	(0x020C) 	/**<  Control Register for CS 0 */
#define SMC_SETUP1 	(0x0210) 	/**<  Setup Register for CS 1 */
#define SMC_PULSE1 	(0x0214) 	/**<  Pulse Register for CS 1 */
#define SMC_CYCLE1 	(0x0218) 	/**<  Cycle Register for CS 1 */
#define SMC_CTRL1 	(0x021C) 	/**<  Control Register for CS 1 */
#define SMC_SETUP2 	(0x0220) 	/**<  Setup Register for CS 2 */
#define SMC_PULSE2 	(0x0224) 	/**<  Pulse Register for CS 2 */
#define SMC_CYCLE2 	(0x0228) 	/**<  Cycle Register for CS 2 */
#define SMC_CTRL2 	(0x022C) 	/**<  Control Register for CS 2 */
#define SMC_SETUP3 	(0x0230) 	/**<  Setup Register for CS 3 */
#define SMC_PULSE3 	(0x0234) 	/**<  Pulse Register for CS 3 */
#define SMC_CYCLE3 	(0x0238) 	/**<  Cycle Register for CS 3 */
#define SMC_CTRL3 	(0x023C) 	/**<  Control Register for CS 3 */
#define SMC_SETUP4 	(0x0240) 	/**<  Setup Register for CS 4 */
#define SMC_PULSE4 	(0x0244) 	/**<  Pulse Register for CS 4 */
#define SMC_CYCLE4 	(0x0248) 	/**<  Cycle Register for CS 4 */
#define SMC_CTRL4 	(0x024C) 	/**<  Control Register for CS 4 */
#define SMC_SETUP5 	(0x0250) 	/**<  Setup Register for CS 5 */
#define SMC_PULSE5 	(0x0254) 	/**<  Pulse Register for CS 5 */
#define SMC_CYCLE5 	(0x0258) 	/**<  Cycle Register for CS 5 */
#define SMC_CTRL5 	(0x025C) 	/**<  Control Register for CS 5 */
#define SMC_SETUP6 	(0x0260) 	/**<  Setup Register for CS 6 */
#define SMC_PULSE6 	(0x0264) 	/**<  Pulse Register for CS 6 */
#define SMC_CYCLE6 	(0x0268) 	/**<  Cycle Register for CS 6 */
#define SMC_CTRL6 	(0x026C) 	/**<  Control Register for CS 6 */
#define SMC_SETUP7 	(0x0270) 	/**<  Setup Register for CS 7 */
#define SMC_PULSE7 	(0x0274) 	/**<  Pulse Register for CS 7 */
#define SMC_CYCLE7 	(0x0278) 	/**<  Cycle Register for CS 7 */
#define SMC_CTRL7 	(0x027C) 	/**<  Control Register for CS 7 */
#define MATRIX_MCFG0 	(0x0400) 	/**<  Master Configuration Register 0 (ram96k)      */
#define MATRIX_MCFG1 	(0x0404) 	/**<  Master Configuration Register 1 (rom)     */
#define MATRIX_MCFG2 	(0x0408) 	/**<  Master Configuration Register 2 (hperiphs)  */
#define MATRIX_MCFG3 	(0x040C) 	/**<  Master Configuration Register 3 (ebi) */
#define MATRIX_MCFG4 	(0x0410) 	/**<  Master Configuration Register 4 (bridge)     */
#define MATRIX_MCFG5 	(0x0414) 	/**<  Master Configuration Register 5 (mailbox)     */
#define MATRIX_MCFG6 	(0x0418) 	/**<  Master Configuration Register 6 (ram16k)   */
#define MATRIX_MCFG7 	(0x041C) 	/**<  Master Configuration Register 7 (teak_prog)      */
#define MATRIX_SCFG0 	(0x0440) 	/**<  Slave Configuration Register 0 (ram96k)      */
#define MATRIX_SCFG1 	(0x0444) 	/**<  Slave Configuration Register 1 (rom)     */
#define MATRIX_SCFG2 	(0x0448) 	/**<  Slave Configuration Register 2 (hperiphs)  */
#define MATRIX_SCFG3 	(0x044C) 	/**<  Slave Configuration Register 3 (ebi) */
#define MATRIX_SCFG4 	(0x0450) 	/**<  Slave Configuration Register 4 (bridge)     */
#define MATRIX_PRAS0 	(0x0480) 	/**<  PRAS0 (ram0)  */
#define MATRIX_PRBS0 	(0x0484) 	/**<  PRBS0 (ram0)  */
#define MATRIX_PRAS1 	(0x0488) 	/**<  PRAS1 (ram1)  */
#define MATRIX_PRBS1 	(0x048C) 	/**<  PRBS1 (ram1)  */
#define MATRIX_PRAS2 	(0x0490) 	/**<  PRAS2 (ram2)  */
#define MATRIX_PRBS2 	(0x0494) 	/**<  PRBS2 (ram2)  */
#define MATRIX_MRCR 	(0x0500) 	/**<  Master Remp Control Register  */
#define CCFG_EBICSA 	(0x051C) 	/**<  EBI Chip Select Assignement Register */
#define MATRIX_TEAKCFG 	(0x052C) 	/**<  Slave 7 (teak_prog) Special Function Register */
#define CCFG_MATRIXVERSION 	(0x05FC) 	/**<  Version Register */
#define AIC_SMR 	(0x0600) 	/**< Source Mode Register */
#define AIC_SVR 	(0x0680) 	/**< Source Vector Register */
#define AIC_IVR 	(0x0700) 	/**< IRQ Vector Register */
#define AIC_FVR 	(0x0704) 	/**< FIQ Vector Register */
#define AIC_ISR 	(0x0708) 	/**< Interrupt Status Register */
#define AIC_IPR 	(0x070C) 	/**< Interrupt Pending Register */
#define AIC_IMR 	(0x0710) 	/**< Interrupt Mask Register */
#define AIC_CISR 	(0x0714) 	/**< Core Interrupt Status Register */
#define AIC_IECR 	(0x0720) 	/**< Interrupt Enable Command Register */
#define AIC_IDCR 	(0x0724) 	/**< Interrupt Disable Command Register */
#define AIC_ICCR 	(0x0728) 	/**< Interrupt Clear Command Register */
#define AIC_ISCR 	(0x072C) 	/**< Interrupt Set Command Register */
#define AIC_EOICR 	(0x0730) 	/**< End of Interrupt Command Register */
#define AIC_SPU 	(0x0734) 	/**< Spurious Vector Register */
#define AIC_DCR 	(0x0738) 	/**< Debug Control Register (Protect) */
#define AIC_FFER 	(0x0740) 	/**< Fast Forcing Enable Register */
#define AIC_FFDR 	(0x0744) 	/**< Fast Forcing Disable Register */
#define AIC_FFSR 	(0x0748) 	/**< Fast Forcing Status Register */
#define DBGU_CR 	(0x0800) 	/**< Control Register */
#define DBGU_MR 	(0x0804) 	/**< Mode Register */
#define DBGU_IER 	(0x0808) 	/**< Interrupt Enable Register */
#define DBGU_IDR 	(0x080C) 	/**< Interrupt Disable Register */
#define DBGU_IMR 	(0x0810) 	/**< Interrupt Mask Register */
#define DBGU_CSR 	(0x0814) 	/**< Channel Status Register */
#define DBGU_RHR 	(0x0818) 	/**< Receiver Holding Register */
#define DBGU_THR 	(0x081C) 	/**< Transmitter Holding Register */
#define DBGU_BRGR 	(0x0820) 	/**< Baud Rate Generator Register */
#define DBGU_CIDR 	(0x0840) 	/**< Chip ID Register */
#define DBGU_EXID 	(0x0844) 	/**< Chip ID Extension Register */
#define DBGU_FNTR 	(0x0848) 	/**< Force NTRST Register */
#define DBGU_RPR 	(0x0900) 	/**< Receive Pointer Register */
#define DBGU_RCR 	(0x0904) 	/**< Receive Counter Register */