at91sam9260_mci.h

ATMEL AT91SAM9260的中段控制程序！

#define AT91C_MCI_SPCMD       (0x7 << 8 ) /**< (MCI) Special CMD */
#define 	AT91C_MCI_SPCMD_NONE                 (0x0 <<  8) /**< (MCI) Not a special CMD */
#define 	AT91C_MCI_SPCMD_INIT                 (0x1 <<  8) /**< (MCI) Initialization CMD */
#define 	AT91C_MCI_SPCMD_SYNC                 (0x2 <<  8) /**< (MCI) Synchronized CMD */
#define 	AT91C_MCI_SPCMD_IT_CMD               (0x4 <<  8) /**< (MCI) Interrupt command */
#define 	AT91C_MCI_SPCMD_IT_REP               (0x5 <<  8) /**< (MCI) Interrupt response */
#define AT91C_MCI_OPDCMD      (0x1 << 11) /**< (MCI) Open Drain Command */
#define AT91C_MCI_MAXLAT      (0x1 << 12) /**< (MCI) Maximum Latency for Command to respond */
#define AT91C_MCI_TRCMD       (0x3 << 16) /**< (MCI) Transfer CMD */
#define 	AT91C_MCI_TRCMD_NO                   (0x0 << 16) /**< (MCI) No transfer */
#define 	AT91C_MCI_TRCMD_START                (0x1 << 16) /**< (MCI) Start transfer */
#define 	AT91C_MCI_TRCMD_STOP                 (0x2 << 16) /**< (MCI) Stop transfer */
#define AT91C_MCI_TRDIR       (0x1 << 18) /**< (MCI) Transfer Direction */
#define AT91C_MCI_TRTYP       (0x7 << 19) /**< (MCI) Transfer Type */
#define 	AT91C_MCI_TRTYP_BLOCK                (0x0 << 19) /**< (MCI) MMC/SDCard Single Block Transfer type */
#define 	AT91C_MCI_TRTYP_MULTIPLE             (0x1 << 19) /**< (MCI) MMC/SDCard Multiple Block transfer type */
#define 	AT91C_MCI_TRTYP_STREAM               (0x2 << 19) /**< (MCI) MMC Stream transfer type */
#define 	AT91C_MCI_TRTYP_SDIO_BYTE            (0x4 << 19) /**< (MCI) SDIO Byte transfer type */
#define 	AT91C_MCI_TRTYP_SDIO_BLOCK           (0x5 << 19) /**< (MCI) SDIO Block transfer type */
#define AT91C_MCI_IOSPCMD     (0x3 << 24) /**< (MCI) SDIO Special Command */
#define 	AT91C_MCI_IOSPCMD_NONE                 (0x0 << 24) /**< (MCI) NOT a special command */
#define 	AT91C_MCI_IOSPCMD_SUSPEND              (0x1 << 24) /**< (MCI) SDIO Suspend Command */
#define 	AT91C_MCI_IOSPCMD_RESUME               (0x2 << 24) /**< (MCI) SDIO Resume Command */
/* --- Register MCI_BLKR */
#define AT91C_MCI_BCNT        (0xFFFF << 0 ) /**< (MCI) MMC/SDIO Block Count / SDIO Byte Count */
#define AT91C_MCI_BLKLEN      (0xFFFF << 16) /**< (MCI) Data Block Length */
/* --- Register MCI_SR */
#define AT91C_MCI_CMDRDY      (0x1 << 0 ) /**< (MCI) Command Ready flag */
#define AT91C_MCI_RXRDY       (0x1 << 1 ) /**< (MCI) RX Ready flag */
#define AT91C_MCI_TXRDY       (0x1 << 2 ) /**< (MCI) TX Ready flag */
#define AT91C_MCI_BLKE        (0x1 << 3 ) /**< (MCI) Data Block Transfer Ended flag */
#define AT91C_MCI_DTIP        (0x1 << 4 ) /**< (MCI) Data Transfer in Progress flag */
#define AT91C_MCI_NOTBUSY     (0x1 << 5 ) /**< (MCI) Data Line Not Busy flag */
#define AT91C_MCI_ENDRX       (0x1 << 6 ) /**< (MCI) End of RX Buffer flag */
#define AT91C_MCI_ENDTX       (0x1 << 7 ) /**< (MCI) End of TX Buffer flag */
#define AT91C_MCI_SDIOIRQA    (0x1 << 8 ) /**< (MCI) SDIO Interrupt for Slot A */
#define AT91C_MCI_SDIOIRQB    (0x1 << 9 ) /**< (MCI) SDIO Interrupt for Slot B */
#define AT91C_MCI_SDIOIRQC    (0x1 << 10) /**< (MCI) SDIO Interrupt for Slot C */
#define AT91C_MCI_SDIOIRQD    (0x1 << 11) /**< (MCI) SDIO Interrupt for Slot D */
#define AT91C_MCI_RXBUFF      (0x1 << 14) /**< (MCI) RX Buffer Full flag */
#define AT91C_MCI_TXBUFE      (0x1 << 15) /**< (MCI) TX Buffer Empty flag */
#define AT91C_MCI_RINDE       (0x1 << 16) /**< (MCI) Response Index Error flag */
#define AT91C_MCI_RDIRE       (0x1 << 17) /**< (MCI) Response Direction Error flag */
#define AT91C_MCI_RCRCE       (0x1 << 18) /**< (MCI) Response CRC Error flag */
#define AT91C_MCI_RENDE       (0x1 << 19) /**< (MCI) Response End Bit Error flag */
#define AT91C_MCI_RTOE        (0x1 << 20) /**< (MCI) Response Time-out Error flag */
#define AT91C_MCI_DCRCE       (0x1 << 21) /**< (MCI) data CRC Error flag */
#define AT91C_MCI_DTOE        (0x1 << 22) /**< (MCI) Data timeout Error flag */
#define AT91C_MCI_OVRE        (0x1 << 30) /**< (MCI) Overrun flag */
#define AT91C_MCI_UNRE        (0x1 << 31) /**< (MCI) Underrun flag */
/* --- Register MCI_IER */
#define AT91C_MCI_CMDRDY      (0x1 << 0 ) /**< (MCI) Command Ready flag */
#define AT91C_MCI_RXRDY       (0x1 << 1 ) /**< (MCI) RX Ready flag */
#define AT91C_MCI_TXRDY       (0x1 << 2 ) /**< (MCI) TX Ready flag */
#define AT91C_MCI_BLKE        (0x1 << 3 ) /**< (MCI) Data Block Transfer Ended flag */
#define AT91C_MCI_DTIP        (0x1 << 4 ) /**< (MCI) Data Transfer in Progress flag */
#define AT91C_MCI_NOTBUSY     (0x1 << 5 ) /**< (MCI) Data Line Not Busy flag */
#define AT91C_MCI_ENDRX       (0x1 << 6 ) /**< (MCI) End of RX Buffer flag */
#define AT91C_MCI_ENDTX       (0x1 << 7 ) /**< (MCI) End of TX Buffer flag */
#define AT91C_MCI_SDIOIRQA    (0x1 << 8 ) /**< (MCI) SDIO Interrupt for Slot A */
#define AT91C_MCI_SDIOIRQB    (0x1 << 9 ) /**< (MCI) SDIO Interrupt for Slot B */
#define AT91C_MCI_SDIOIRQC    (0x1 << 10) /**< (MCI) SDIO Interrupt for Slot C */
#define AT91C_MCI_SDIOIRQD    (0x1 << 11) /**< (MCI) SDIO Interrupt for Slot D */
#define AT91C_MCI_RXBUFF      (0x1 << 14) /**< (MCI) RX Buffer Full flag */
#define AT91C_MCI_TXBUFE      (0x1 << 15) /**< (MCI) TX Buffer Empty flag */
#define AT91C_MCI_RINDE       (0x1 << 16) /**< (MCI) Response Index Error flag */
#define AT91C_MCI_RDIRE       (0x1 << 17) /**< (MCI) Response Direction Error flag */
#define AT91C_MCI_RCRCE       (0x1 << 18) /**< (MCI) Response CRC Error flag */
#define AT91C_MCI_RENDE       (0x1 << 19) /**< (MCI) Response End Bit Error flag */
#define AT91C_MCI_RTOE        (0x1 << 20) /**< (MCI) Response Time-out Error flag */
#define AT91C_MCI_DCRCE       (0x1 << 21) /**< (MCI) data CRC Error flag */
#define AT91C_MCI_DTOE        (0x1 << 22) /**< (MCI) Data timeout Error flag */
#define AT91C_MCI_OVRE        (0x1 << 30) /**< (MCI) Overrun flag */
#define AT91C_MCI_UNRE        (0x1 << 31) /**< (MCI) Underrun flag */
/* --- Register MCI_IDR */
#define AT91C_MCI_CMDRDY      (0x1 << 0 ) /**< (MCI) Command Ready flag */
#define AT91C_MCI_RXRDY       (0x1 << 1 ) /**< (MCI) RX Ready flag */
#define AT91C_MCI_TXRDY       (0x1 << 2 ) /**< (MCI) TX Ready flag */
#define AT91C_MCI_BLKE        (0x1 << 3 ) /**< (MCI) Data Block Transfer Ended flag */
#define AT91C_MCI_DTIP        (0x1 << 4 ) /**< (MCI) Data Transfer in Progress flag */
#define AT91C_MCI_NOTBUSY     (0x1 << 5 ) /**< (MCI) Data Line Not Busy flag */
#define AT91C_MCI_ENDRX       (0x1 << 6 ) /**< (MCI) End of RX Buffer flag */
#define AT91C_MCI_ENDTX       (0x1 << 7 ) /**< (MCI) End of TX Buffer flag */
#define AT91C_MCI_SDIOIRQA    (0x1 << 8 ) /**< (MCI) SDIO Interrupt for Slot A */
#define AT91C_MCI_SDIOIRQB    (0x1 << 9 ) /**< (MCI) SDIO Interrupt for Slot B */
#define AT91C_MCI_SDIOIRQC    (0x1 << 10) /**< (MCI) SDIO Interrupt for Slot C */
#define AT91C_MCI_SDIOIRQD    (0x1 << 11) /**< (MCI) SDIO Interrupt for Slot D */
#define AT91C_MCI_RXBUFF      (0x1 << 14) /**< (MCI) RX Buffer Full flag */
#define AT91C_MCI_TXBUFE      (0x1 << 15) /**< (MCI) TX Buffer Empty flag */
#define AT91C_MCI_RINDE       (0x1 << 16) /**< (MCI) Response Index Error flag */
#define AT91C_MCI_RDIRE       (0x1 << 17) /**< (MCI) Response Direction Error flag */
#define AT91C_MCI_RCRCE       (0x1 << 18) /**< (MCI) Response CRC Error flag */
#define AT91C_MCI_RENDE       (0x1 << 19) /**< (MCI) Response End Bit Error flag */
#define AT91C_MCI_RTOE        (0x1 << 20) /**< (MCI) Response Time-out Error flag */
#define AT91C_MCI_DCRCE       (0x1 << 21) /**< (MCI) data CRC Error flag */
#define AT91C_MCI_DTOE        (0x1 << 22) /**< (MCI) Data timeout Error flag */
#define AT91C_MCI_OVRE        (0x1 << 30) /**< (MCI) Overrun flag */
#define AT91C_MCI_UNRE        (0x1 << 31) /**< (MCI) Underrun flag */
/* --- Register MCI_IMR */
#define AT91C_MCI_CMDRDY      (0x1 << 0 ) /**< (MCI) Command Ready flag */
#define AT91C_MCI_RXRDY       (0x1 << 1 ) /**< (MCI) RX Ready flag */
#define AT91C_MCI_TXRDY       (0x1 << 2 ) /**< (MCI) TX Ready flag */
#define AT91C_MCI_BLKE        (0x1 << 3 ) /**< (MCI) Data Block Transfer Ended flag */
#define AT91C_MCI_DTIP        (0x1 << 4 ) /**< (MCI) Data Transfer in Progress flag */
#define AT91C_MCI_NOTBUSY     (0x1 << 5 ) /**< (MCI) Data Line Not Busy flag */
#define AT91C_MCI_ENDRX       (0x1 << 6 ) /**< (MCI) End of RX Buffer flag */
#define AT91C_MCI_ENDTX       (0x1 << 7 ) /**< (MCI) End of TX Buffer flag */
#define AT91C_MCI_SDIOIRQA    (0x1 << 8 ) /**< (MCI) SDIO Interrupt for Slot A */
#define AT91C_MCI_SDIOIRQB    (0x1 << 9 ) /**< (MCI) SDIO Interrupt for Slot B */
#define AT91C_MCI_SDIOIRQC    (0x1 << 10) /**< (MCI) SDIO Interrupt for Slot C */
#define AT91C_MCI_SDIOIRQD    (0x1 << 11) /**< (MCI) SDIO Interrupt for Slot D */
#define AT91C_MCI_RXBUFF      (0x1 << 14) /**< (MCI) RX Buffer Full flag */
#define AT91C_MCI_TXBUFE      (0x1 << 15) /**< (MCI) TX Buffer Empty flag */
#define AT91C_MCI_RINDE       (0x1 << 16) /**< (MCI) Response Index Error flag */
#define AT91C_MCI_RDIRE       (0x1 << 17) /**< (MCI) Response Direction Error flag */
#define AT91C_MCI_RCRCE       (0x1 << 18) /**< (MCI) Response CRC Error flag */
#define AT91C_MCI_RENDE       (0x1 << 19) /**< (MCI) Response End Bit Error flag */
#define AT91C_MCI_RTOE        (0x1 << 20) /**< (MCI) Response Time-out Error flag */
#define AT91C_MCI_DCRCE       (0x1 << 21) /**< (MCI) data CRC Error flag */
#define AT91C_MCI_DTOE        (0x1 << 22) /**< (MCI) Data timeout Error flag */
#define AT91C_MCI_OVRE        (0x1 << 30) /**< (MCI) Overrun flag */
#define AT91C_MCI_UNRE        (0x1 << 31) /**< (MCI) Underrun flag */

#endif /* __AT91SAM9260_MCI_H */