📄 at91sam9260.h
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AT91_REG PIOA_IFSR; // Input Filter Status Register
AT91_REG Reserved19[1]; //
AT91_REG PIOA_SODR; // Set Output Data Register
AT91_REG PIOA_CODR; // Clear Output Data Register
AT91_REG PIOA_ODSR; // Output Data Status Register
AT91_REG PIOA_PDSR; // Pin Data Status Register
AT91_REG PIOA_IER; // Interrupt Enable Register
AT91_REG PIOA_IDR; // Interrupt Disable Register
AT91_REG PIOA_IMR; // Interrupt Mask Register
AT91_REG PIOA_ISR; // Interrupt Status Register
AT91_REG PIOA_MDER; // Multi-driver Enable Register
AT91_REG PIOA_MDDR; // Multi-driver Disable Register
AT91_REG PIOA_MDSR; // Multi-driver Status Register
AT91_REG Reserved20[1]; //
AT91_REG PIOA_PPUDR; // Pull-up Disable Register
AT91_REG PIOA_PPUER; // Pull-up Enable Register
AT91_REG PIOA_PPUSR; // Pull-up Status Register
AT91_REG Reserved21[1]; //
AT91_REG PIOA_ASR; // Select A Register
AT91_REG PIOA_BSR; // Select B Register
AT91_REG PIOA_ABSR; // AB Select Status Register
AT91_REG Reserved22[9]; //
AT91_REG PIOA_OWER; // Output Write Enable Register
AT91_REG PIOA_OWDR; // Output Write Disable Register
AT91_REG PIOA_OWSR; // Output Write Status Register
AT91_REG Reserved23[85]; //
AT91_REG PIOB_PER; // PIO Enable Register
AT91_REG PIOB_PDR; // PIO Disable Register
AT91_REG PIOB_PSR; // PIO Status Register
AT91_REG Reserved24[1]; //
AT91_REG PIOB_OER; // Output Enable Register
AT91_REG PIOB_ODR; // Output Disable Registerr
AT91_REG PIOB_OSR; // Output Status Register
AT91_REG Reserved25[1]; //
AT91_REG PIOB_IFER; // Input Filter Enable Register
AT91_REG PIOB_IFDR; // Input Filter Disable Register
AT91_REG PIOB_IFSR; // Input Filter Status Register
AT91_REG Reserved26[1]; //
AT91_REG PIOB_SODR; // Set Output Data Register
AT91_REG PIOB_CODR; // Clear Output Data Register
AT91_REG PIOB_ODSR; // Output Data Status Register
AT91_REG PIOB_PDSR; // Pin Data Status Register
AT91_REG PIOB_IER; // Interrupt Enable Register
AT91_REG PIOB_IDR; // Interrupt Disable Register
AT91_REG PIOB_IMR; // Interrupt Mask Register
AT91_REG PIOB_ISR; // Interrupt Status Register
AT91_REG PIOB_MDER; // Multi-driver Enable Register
AT91_REG PIOB_MDDR; // Multi-driver Disable Register
AT91_REG PIOB_MDSR; // Multi-driver Status Register
AT91_REG Reserved27[1]; //
AT91_REG PIOB_PPUDR; // Pull-up Disable Register
AT91_REG PIOB_PPUER; // Pull-up Enable Register
AT91_REG PIOB_PPUSR; // Pull-up Status Register
AT91_REG Reserved28[1]; //
AT91_REG PIOB_ASR; // Select A Register
AT91_REG PIOB_BSR; // Select B Register
AT91_REG PIOB_ABSR; // AB Select Status Register
AT91_REG Reserved29[9]; //
AT91_REG PIOB_OWER; // Output Write Enable Register
AT91_REG PIOB_OWDR; // Output Write Disable Register
AT91_REG PIOB_OWSR; // Output Write Status Register
AT91_REG Reserved30[85]; //
AT91_REG PIOC_PER; // PIO Enable Register
AT91_REG PIOC_PDR; // PIO Disable Register
AT91_REG PIOC_PSR; // PIO Status Register
AT91_REG Reserved31[1]; //
AT91_REG PIOC_OER; // Output Enable Register
AT91_REG PIOC_ODR; // Output Disable Registerr
AT91_REG PIOC_OSR; // Output Status Register
AT91_REG Reserved32[1]; //
AT91_REG PIOC_IFER; // Input Filter Enable Register
AT91_REG PIOC_IFDR; // Input Filter Disable Register
AT91_REG PIOC_IFSR; // Input Filter Status Register
AT91_REG Reserved33[1]; //
AT91_REG PIOC_SODR; // Set Output Data Register
AT91_REG PIOC_CODR; // Clear Output Data Register
AT91_REG PIOC_ODSR; // Output Data Status Register
AT91_REG PIOC_PDSR; // Pin Data Status Register
AT91_REG PIOC_IER; // Interrupt Enable Register
AT91_REG PIOC_IDR; // Interrupt Disable Register
AT91_REG PIOC_IMR; // Interrupt Mask Register
AT91_REG PIOC_ISR; // Interrupt Status Register
AT91_REG PIOC_MDER; // Multi-driver Enable Register
AT91_REG PIOC_MDDR; // Multi-driver Disable Register
AT91_REG PIOC_MDSR; // Multi-driver Status Register
AT91_REG Reserved34[1]; //
AT91_REG PIOC_PPUDR; // Pull-up Disable Register
AT91_REG PIOC_PPUER; // Pull-up Enable Register
AT91_REG PIOC_PPUSR; // Pull-up Status Register
AT91_REG Reserved35[1]; //
AT91_REG PIOC_ASR; // Select A Register
AT91_REG PIOC_BSR; // Select B Register
AT91_REG PIOC_ABSR; // AB Select Status Register
AT91_REG Reserved36[9]; //
AT91_REG PIOC_OWER; // Output Write Enable Register
AT91_REG PIOC_OWDR; // Output Write Disable Register
AT91_REG PIOC_OWSR; // Output Write Status Register
AT91_REG Reserved37[213]; //
AT91_REG PMC_SCER; // System Clock Enable Register
AT91_REG PMC_SCDR; // System Clock Disable Register
AT91_REG PMC_SCSR; // System Clock Status Register
AT91_REG Reserved38[1]; //
AT91_REG PMC_PCER; // Peripheral Clock Enable Register
AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
AT91_REG PMC_PCSR; // Peripheral Clock Status Register
AT91_REG Reserved39[1]; //
AT91_REG PMC_MOR; // Main Oscillator Register
AT91_REG PMC_MCFR; // Main Clock Frequency Register
AT91_REG PMC_PLLAR; // PLL A Register
AT91_REG PMC_PLLBR; // PLL B Register
AT91_REG PMC_MCKR; // Master Clock Register
AT91_REG Reserved40[3]; //
AT91_REG PMC_PCKR[8]; // Programmable Clock Register
AT91_REG PMC_IER; // Interrupt Enable Register
AT91_REG PMC_IDR; // Interrupt Disable Register
AT91_REG PMC_SR; // Status Register
AT91_REG PMC_IMR; // Interrupt Mask Register
AT91_REG Reserved41[36]; //
AT91_REG RSTC_RCR; // Reset Control Register
AT91_REG RSTC_RSR; // Reset Status Register
AT91_REG RSTC_RMR; // Reset Mode Register
AT91_REG Reserved42[1]; //
AT91_REG SHDWC_SHCR; // Shut Down Control Register
AT91_REG SHDWC_SHMR; // Shut Down Mode Register
AT91_REG SHDWC_SHSR; // Shut Down Status Register
AT91_REG Reserved43[1]; //
AT91_REG RTTC_RTMR; // Real-time Mode Register
AT91_REG RTTC_RTAR; // Real-time Alarm Register
AT91_REG RTTC_RTVR; // Real-time Value Register
AT91_REG RTTC_RTSR; // Real-time Status Register
AT91_REG PITC_PIMR; // Period Interval Mode Register
AT91_REG PITC_PISR; // Period Interval Status Register
AT91_REG PITC_PIVR; // Period Interval Value Register
AT91_REG PITC_PIIR; // Period Interval Image Register
AT91_REG WDTC_WDCR; // Watchdog Control Register
AT91_REG WDTC_WDMR; // Watchdog Mode Register
AT91_REG WDTC_WDSR; // Watchdog Status Register
AT91_REG Reserved44[1]; //
AT91_REG SYS_GPBR0; // General Purpose Register 0
AT91_REG SYS_GPBR1; // General Purpose Register 1
AT91_REG SYS_GPBR2; // General Purpose Register 2
AT91_REG SYS_GPBR3; // General Purpose Register 3
} AT91S_SYS, *AT91PS_SYS;
// -------- GPBR : (SYS Offset: 0x1350) GPBR General Purpose Register --------
// -------- GPBR : (SYS Offset: 0x1354) GPBR General Purpose Register --------
// -------- GPBR : (SYS Offset: 0x1358) GPBR General Purpose Register --------
// -------- GPBR : (SYS Offset: 0x135c) GPBR General Purpose Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface
// *****************************************************************************
typedef struct _AT91S_EBI {
AT91_REG EBI_DUMMY; // Dummy register - Do not use
} AT91S_EBI, *AT91PS_EBI;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Error Correction Code controller
// *****************************************************************************
typedef struct _AT91S_ECC {
AT91_REG ECC_CR; // ECC reset register
AT91_REG ECC_MR; // ECC Page size register
AT91_REG ECC_SR; // ECC Status register
AT91_REG ECC_PR; // ECC Parity register
AT91_REG ECC_NPR; // ECC Parity N register
AT91_REG Reserved0[58]; //
AT91_REG ECC_VR; // ECC Version register
} AT91S_ECC, *AT91PS_ECC;
// -------- ECC_CR : (ECC Offset: 0x0) ECC reset register --------
#define AT91C_ECC_RST ((unsigned int) 0x1 << 0) // (ECC) ECC reset parity
// -------- ECC_MR : (ECC Offset: 0x4) ECC page size register --------
#define AT91C_ECC_PAGE_SIZE ((unsigned int) 0x3 << 0) // (ECC) Nand Flash page size
// -------- ECC_SR : (ECC Offset: 0x8) ECC status register --------
#define AT91C_ECC_RECERR ((unsigned int) 0x1 << 0) // (ECC) ECC error
#define AT91C_ECC_ECCERR ((unsigned int) 0x1 << 1) // (ECC) ECC single error
#define AT91C_ECC_MULERR ((unsigned int) 0x1 << 2) // (ECC) ECC_MULERR
// -------- ECC_PR : (ECC Offset: 0xc) ECC parity register --------
#define AT91C_ECC_BITADDR ((unsigned int) 0xF << 0) // (ECC) Bit address error
#define AT91C_ECC_WORDADDR ((unsigned int) 0xFFF << 4) // (ECC) address of the failing bit
// -------- ECC_NPR : (ECC Offset: 0x10) ECC N parity register --------
#define AT91C_ECC_NPARITY ((unsigned int) 0xFFFF << 0) // (ECC) ECC parity N
// -------- ECC_VR : (ECC Offset: 0xfc) ECC version register --------
#define AT91C_ECC_VR ((unsigned int) 0xF << 0) // (ECC) ECC version register
// *****************************************************************************
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