mmusetup.s

cache test for arm920 core

;**********************************************************************
;                                                                      
; Filename: mmusetup.s
;                                                                      
; Description: Contains the pagetable and mmu setup routines for the
; data abort test.
;
; THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
; ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
; THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
; PARTICULAR PURPOSE.
; Copyright(c) Cirrus Logic Corporation 2001, All Rights Reserved                       
;                                                                      
;**********************************************************************
        include mmusetup.inc
        AREA    PageTable, DATA, READONLY, ALIGN=14

        GBLA    XCount
        

;*************************************************************************
;
;  LevelOnePageTable
;
;  All entries map Linear = Physical.
;
;*************************************************************************
        EXPORT  LevelOnePageTable
LevelOnePageTable
        DCD     (0x00000000 :OR: SECTION_HEADER :OR: WRITE_BACK)

;
; Virtual address  = 0x00000000
; Physical address = 0x00000000
; Size             = 0x80000000              
; Cached write through
;
XCount  SETA    (0x00100000 :OR: SECTION_HEADER :OR: UNCACHED)
        WHILE   XCount < 0x80000000
        DCD     XCount
XCount  SETA    XCount + 0x00100000
        WEND

        DCD     (0x80000000 :OR: SECTION_HEADER :OR: WRITE_BACK)
;
; Virtual address  = 0x80100000
; Physical address = 0x80100000
; Size             = 0x80000000              
; UnCached
;
XCount  SETA (0x80100000 :OR: SECTION_HEADER :OR: UNCACHED)
        WHILE   XCount < 0xFFF00000
        DCD     XCount
XCount  SETA XCount + 0x00100000
        WEND
        DCD     0xfff00c1a

PageTableEnd

LevelTwoCoarsePageTable


;*************************************************************************
;
;  MMUSetup
;
;  Sets up the Page Table and the MMU.
;
;*************************************************************************
        AREA    MMUSetupArea, CODE, READONLY, ALIGN=12
        EXPORT  MMUSetup
MMUSetup
        stmfd  sp!, {lr}

        ;
        ; Set up the MMU.  Start by flushing the cache and TLB.
        ;
        bl      FlushICache
        bl      FlushDCache
        bl      TLBClear

        ;
        ; Set user mode access for all 16 domains.
        ;
        ldr     r0, =0x55555555
        mcr     p15, 0, r0, c3, c0, 0

        ;
        ; Tell the MMU where to find the page table.
        ;
        ldr     r0, =LevelOnePageTable
        mcr     p15, 0, r0, c2, c0, 0

        ;
        ; Enable the MMU.
        ;
        ldr     r0, =0xc000107d
        mcr     p15, 0, r0, c1, c0, 0

        ;
        ; There should always be two NOP instructions following the enable or
        ; disable of the MMU.
        ;
        nop
        nop

        ;;
        ;; Return
        ;;
        ldmfd  sp!, {pc}


;++
; Routine Description:
;    Flush and invalidate the Instruction Cache for ARM920
;
; Syntax:
;       void FlushICache(void);
;
; Arguments:
;       -- none --
;
; Return Value:
;       -- none --
;--
        EXPORT  FlushICache
FlushICache
        mcr     p15, 0, r0, c7, c5, 0   ; flush the icache
        mov     pc, lr                  ; return

;++
; Routine Description:
;    Clean and invalidate the Data Cache
;
; The following code is called to flush the dcache on the ARM920T. It
; does a clean and invalidate on each cache line using the index and
; segment.
;
; Syntax:
;       void FlushDCache(void);
    EXPORT  FlushDCache
FlushDCache

    stmfd   sp!, {r4, lr}
    
    ;
    ; Drain the write buffer.
    ;
    mcr     p15, 0, r0, c7, c10, 4

    ;   
    ; There are 64 cache lines per segment
    ;            
    mov     lr, #0x3f
camloop
    ;
    ; The cache line index goes in the upper 6 bits of the cache line
    ; address
    ;
    mov     r0, lr, lsl #26                 ; CAM index
            
    ;
    ; There are 8 Segments per cache line index
    ;
    mov     r2, #0x7
blockloop
        ;
        ; Calculate the current cache line address to Clean/Invalidate.
        ;
        orr     r4, r0, r2, lsl #5       ; OR in segment number
            
        ;
        ; Clean and Invalidate this Cache Entry
        ;
        mcr     p15, 0, r4, c7, c14, 2   
            
        ; 
        ; Drain write buffer for this Entry.  Why?
        ;
        mcr     p15, 0, r0, c7, c10, 4   
          
        subs    r2, r2, #1
        bpl     blockloop

    subs    lr, lr, #1
    bpl     camloop

    ldmfd   sp!, {r4, pc}

;----------------------------------------------------------------------------------
; GetDirty
;----------------------------------------------------------------------------------
; Just something to make some of the cache dirty.
;----------------------------------------------------------------------------------
    EXPORT GetDirty
GetDirty
    stmfd   sp!, {r0-r12,lr}
    ldmfd   sp!, {r0-r12,pc}    


;++
; Routine Description:
;    Flush and invalidate the Instruction & Data TLBs for the ARM920
;
; Syntax:
;       void TLBClear(void);
;
; Arguments:
;       -- none --
;
; Return Value:
;       -- none --
;--
        EXPORT  TLBClear
TLBClear
    mcr     p15, 0, r0, c8, c5, 0           ; Invalidate I tlb
    mcr     p15, 0, r0, c8, c6, 0           ; Invalidate D tlb
    mov     pc, lr                          ; return

        END