lj.vhd

基于VHDL语言的四状态转换指示灯设计

Library IEEE ;
use IEEE.std_logic_1164.all ;


ENTITY lj IS
	PORT(
		clk		: IN	BIT;
		input	: IN	BIT;
		reset	: IN	BIT;
		output1	: OUT	BIT;
        output2	: OUT	BIT;
        output3	: OUT	BIT;
		output4	: OUT	BIT);
END lj;

ARCHITECTURE a OF lj IS
	TYPE STATE_TYPE IS (s0, s1, s2, s3);
	SIGNAL state	: STATE_TYPE;
BEGIN
	PROCESS (clk)
	BEGIN
		IF reset = '1' THEN
			state <= s0;
		ELSIF (clk'EVENT AND clk = '1') THEN
			CASE state IS
				WHEN s0=>
					state <= s1;
				WHEN s1=>
					state <= s2;				
				WHEN s2=>
					state <= s3;
				WHEN s3=>
					IF input = '1' THEN
						state <= s2;
					ELSE
						state <= s1;
					END IF;
			END CASE;
		END IF;
	END PROCESS;
	
	output1 <= '1' WHEN state = s0 ELSE '0';
	output2 <= '1' WHEN state = s1 ELSE '0';
    output3 <= '1' WHEN state = s2 ELSE '0';
    output4 <= '1' WHEN state = s3 ELSE '0';
END a;