44binit.s

EX44B0开发板BootLoader

;****************************************************
;* NAME    : 44BINIT.S                              *
;* Version : 10.April.2000                          *
;* Description:                                     *
;* C start up codes                                 *
;* Configure memory, Initialize ISR ,stacks         *
;* Initialize C-variables                           *
;* Fill zeros into zero-initialized C-variables     *
;****************************************************

; 请将RO Base设为RELOC_OFS指定的位置，不要另外设置RW Base
; 并将代码烧写至0地址位置
;
; 警告：该文件内的一切初始化代码必须可重定位！！！

RELOC_OFS	EQU 0x0c700000			; relocation offset

	GET option.inc
	GET memcfg.inc

;Cache
SYSCFG		EQU 0x01c00000
NCACHBE0	EQU 0x01c00004

;Memory Controller
REFRESH	    EQU 0x01c80024

;I/O Port
PCONC		EQU 0x01d20010
PDATC		EQU 0x01d20014

;Watchdog timer
WTCON	    EQU	0x01d30000

;Clock Controller
PLLCON	    EQU	0x01d80000
CLKCON	    EQU	0x01d80004
LOCKTIME    EQU	0x01d8000c

;Interrupt Control
INTCON		EQU 0x01e00000
INTPND		EQU	0x01e00004
INTMOD		EQU	0x01e00008
INTMSK		EQU	0x01e0000c
I_ISPR		EQU	0x01e00020
I_CMST		EQU	0x01e0001c

;BDMA destination register
BDIDES0     EQU 0x01f80008
BDIDES1     EQU 0x01f80028

	AREA	Init, CODE, READONLY

	ENTRY
	b		ResetHandler
	ldr		pc,=_ISR_STARTADDRESS + 4
	ldr		pc,=_ISR_STARTADDRESS + 8
	ldr		pc,=_ISR_STARTADDRESS + 12
	ldr		pc,=_ISR_STARTADDRESS + 16
	b		.
	ldr		pc,=_ISR_STARTADDRESS + 24
	ldr		pc,=_ISR_STARTADDRESS + 28

;****************************************************
;*      START                                       *
;****************************************************
ResetHandler
	ldr		r0,=WTCON				;watch dog disable 
	mov		r1,#0x0
	str		r1,[r0]

;	ldr		r0,=INTMSK				;disable all interrupt
;	ldr		r1,=0x07ffffff
;	str		r1,[r0]
;	ldr		r0,=INTCON				;enable IRQ interrupt, vector mode
;	mov		r1,#0
;	str		r1,[r0]
;	ldr		r0,=INTMOD				;all interrupt in IRQ mode
;	str		r1,[r0]

	ldr		r0,=PCONC				;switch off LCD
	ldr		r1,=0xa5aaaaaa
	str		r1,[r0]
	ldr		r0,=PDATC
	mov		r1,#0
	str		r1,[r0]

;****************************************************
;*	Set clock control registers                     *
;****************************************************
	ldr		r0,=LOCKTIME
	ldr		r1,=0xfff
	str		r1,[r0]

	[ PLLONSTART
	ldr		r0,=PLLCON				;temporary setting of PLL
	ldr		r1,=((M_DIV<<12)+(P_DIV<<4)+S_DIV)
	str		r1,[r0]
	]

	ldr		r0,=CLKCON
	ldr		r1,=0x7ff8				;All unit block CLK enable	
	str		r1,[r0]

	ldr		r0,=SYSCFG
	mov		r1,#0x0e				;Enable all cache (R/W)
	str		r1,[r0]
	ldr		r0,=NCACHBE0
	mov		r1,#0xc0000000			;Non-cacheable area: 0x00000000 ~ 0x0c000000
	str		r1,[r0]

;****************************************************
;*  change BDMACON reset value for BDMA             *
;****************************************************
	ldr		r0,=BDIDES0
	ldr		r1,=0x40000000			;BDIDESn reset value should be 0x40000000	 
	str		r1,[r0]

	ldr		r0,=BDIDES1
	ldr		r1,=0x40000000			;BDIDESn reset value should be 0x40000000	 
	str		r1,[r0]

;****************************************************
;*  Set memory control registers                    * 	
;****************************************************
	adr		r0,SMRDATA
	ldmia	r0,{r1-r13}
	ldr		r0,=0x01c80000			;BWSCON Address
	stmia	r0,{r1-r13}

;****************************************************
;*  Initialize stacks                               * 
;****************************************************
	ldr		sp, =0x0c800000

;****************************************************
;*  Zero initialized data                           *
;****************************************************
	IMPORT	|Image$$ZI$$Base|
	IMPORT	|Image$$ZI$$Limit|
	IMPORT	Main

	MOV		r0, #0
	LDR		r1, =RELOC_OFS
	LDR		r2, =|Image$$ZI$$Base|
0
	LDMIA	r0!, {r4-r11}
	STMIA	r1!, {r4-r11}
	CMP		r1, r2
	BLO		%B0

	LDR		r3, =|Image$$ZI$$Limit|
	MOV		r0, #0
1
	CMP		r2, r3
	STRLO	r0, [r2], #4
	BLO		%B1

	LDR		pc, =Main

SMRDATA
;*****************************************************************
;* Memory configuration has to be optimized for best performance *
;* The following parameter is not optimized.                     *
;*****************************************************************

;*** memory access cycle parameter strategy ***
; 1) Even FP-DRAM, EDO setting has more late fetch point by half-clock
; 2) The memory settings,here, are made the safe parameters even at 66Mhz.
; 3) FP-DRAM Parameters:tRCD=3 for tRAC, tcas=2 for pad delay, tcp=2 for bus load.
; 4) DRAM refresh rate is for 40Mhz. 

    [ BUSWIDTH=16
	DCD 0x11111110	;Bank0=OM[1:0], Bank1~Bank7=16bit
    | ;BUSWIDTH=32
	DCD 0x22222220	;Bank0=OM[1:0], Bank1~Bank7=32bit
    ]
	DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))	;GCS0
	DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))	;GCS1 
	DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))	;GCS2
	DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))	;GCS3
	DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))	;GCS4
	DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))	;GCS5
	[ BDRAMTYPE="DRAM" 
	    DCD ((B6_MT<<15)+(B6_Trcd<<4)+(B6_Tcas<<3)+(B6_Tcp<<2)+(B6_CAN))	;GCS6 check the MT value in parameter.a
	    DCD ((B7_MT<<15)+(B7_Trcd<<4)+(B7_Tcas<<3)+(B7_Tcp<<2)+(B7_CAN))	;GCS7
	| ;"SDRAM"
		DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))	;GCS6
		DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))	;GCS7
	]
	DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)	;REFRESH RFEN=1, TREFMD=0, trp=3clk, trc=5clk, tchr=3clk,count=1019
	DCD 0x10			;SCLK power down mode, BANKSIZE 32M/32M
	DCD 0x20			;MRSR6 CL=2clk
	DCD 0x20			;MRSR7

    LTORG

	END