head.s

基于S3C2410的xmodem协议实现

@ Start of executable code 

#include "config.h"

.global _start

_start:

@ Exception vector table (physical address = 0x00000000)

	b	Reset
	b	.
  b	.
	b	.
	b	.
	b	.
	b	.
	b	.

@ Start VIVI head

Reset:
	@ disable watch dog timer
	mov	r1, #WTCON
	mov	r2, #0x0
	str	r2, [r1]

	@ disable all interrupts
	mov	r1, #INT_CTL_BASE
	mov	r2, #0xffffffff
	str	r2, [r1, #oINTMSK]
	ldr	r2, =0x7ff
	str	r2, [r1, #oINTSUBMSK]	
	
	@ initialise system clocks
	mov	r1, #INT_CTL_BASE
	mvn	r2, #0xff000000
	str	r2, [r1, #oLOCKTIME]

	mov	r1, #CLK_CTL_BASE
	mov	r2, #0x3
	str	r2, [r1, #0x14]

	mrc	p15, 0, r1, c1, c0, 0		@ read ctrl register 
	orr	r1, r1, #0xc0000000		@ Asynchronous  
	mcr	p15, 0, r1, c1, c0, 0		@ write ctrl register
	
	@ now ,usb clock is 48Mhz
	ldr     r0, =CLK_CTL_BASE  @ Fin=12MHz, Fout=48MHz
	ldr     r1, =upp_48Mhz 
	str     r1, [r0,#0x08]
 
 	nop
 	nop
 	nop
 	nop
 	ldr     r0, =CLK_CTL_BASE  @ Fin=12MHz, Fout=48MHz
	ldr     r1, =upp_48Mhz 
	str     r1, [r0,#0x08] 

	@ now, CPU clock is 200 Mhz
	mov	r1, #CLK_CTL_BASE
	ldr	r2, =mpll_200mhz
	str	r2, [r1, #oMPLLCON]
	
	@ All LED on
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_F
	ldr	r2,=0x55aa
	str	r2, [r1, #oGPIO_A]
	mov	r2, #0xff
	str	r2, [r1, #oGPIO_UP]
	mov	r2, #0x00
	str	r2, [r1, #oGPIO_DAT]	

	bl	memsetup
	
	ldr sp, = SDRAM_END

	bl main

die:
	b die

memsetup:
	@ set memory control registers
	mov	r1, #0x48000000
	adrl	r2, mem_cfg_val
	add	r3, r1, #52
1:	
	ldr	r4, [r2], #4
	str	r4, [r1], #4
	cmp	r1, r3
	bne	1b

	mov	pc, lr
	
@
@ Data Area
@
@ Memory configuration values
.align 4
mem_cfg_val:
	.long	vBWSCON
	.long	vBANKCON0
	.long	vBANKCON1
	.long	vBANKCON2
	.long	vBANKCON3
	.long	vBANKCON4
	.long	vBANKCON5
	.long	vBANKCON6
	.long	vBANKCON7
	.long	vREFRESH
	.long	vBANKSIZE
	.long	vMRSRB6
	.long	vMRSRB7