sbq.vhd

07全国大学生电子设计竞赛C题获奖作品FPGA核心部分源码（EP1C6Q）

LIBRARY	IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.std_logic_arith.all;

ENTITY sbq	IS
PORT (sysclk,tset,tctrl,sxin,dccf,chf,cc,xs,kz: in std_logic;
	jzclk,sxout,sxfko,ctrlnclk:out std_logic;
	ctrlclk:buffer std_logic;
	din:in std_logic_vector (7 downto 0);
	do,rdadd:out STD_LOGIC_VECTOR (7 DOWNTO 0) );	
END sbq;

architecture sbq of sbq is
	type ram is array(255 downto 0) of std_logic_vector(7 downto 0);
	signal  dualram,dualram1 :      ram;
--	signal  dualram,dualram1 :array(255 downto 0) of std_logic_vector(7 downto 0);
	signal ct0,ct2,ct3,ct4,ct5,cnt6,ct6:std_logic;
	signal wrclk,rdclk: std_logic;
	signal wable,wable1: std_logic;
	signal dout,dout1: STD_LOGIC_VECTOR (7 DOWNTO 0);
	signal wadd,radd,wadd1:std_logic_vector(7 downto 0);
	signal wdc,wctrl,wctrl1,wdc1:std_logic;
	signal cnt0:std_logic_vector(3 downto 0);
	signal cnt5:std_logic_vector(3 downto 0);
	signal cnt1:std_logic_vector(5 downto 0);
	signal cnt2:std_logic_vector(6 downto 0);
	signal cnt3:std_logic_vector(3 downto 0);
	signal cnt4:std_logic_vector(7 downto 0);
	signal sxc:std_logic_vector(3 downto 0);
	signal sxfk:std_logic;
begin
	fenpin0:process(sysclk)
	begin
		if rising_edge(sysclk) then
--cnt0 1/40 sysclk 1Mhz
			if cnt0="1001" then
				ct0<=not ct0;
				cnt0<="0000";
--cnt5 1/400 sysclk 100Khz
				if cnt5="1001" then
					ct5<=not ct5;
					cnt5<="0000";
--cnt1 1/16K sysclk 2.5Khz
					if cnt1="100111" then
						rdclk<=not rdclk;
						cnt1<="000000";
					else
						cnt1<=cnt1 +1;
					end if;
--cnt2 1/40K sysclk 1Khz 
					if cnt2="1100011" then
						ct2<=not ct2;
						cnt2<="0000000";	
					else
						cnt2<=cnt2 +1;
					end if;
				else
					cnt5<=cnt5 +1;
				end if;
			else
				cnt0<=cnt0 +1;
			end if;
--cnt3 1/22 sysclk
			if cnt3="1010"	then
				ct3<=not ct3;
				cnt3<="0000";
			else
				cnt3<=cnt3 +1;
			end if;
--cnt4 1/402 sysclk
			if cnt4="11001000" then
				ct4<=not ct4;
				cnt4<="00000000";
			else
				cnt4<=cnt4 +1;
			end if;
			if cnt6='1' then
				ct6<=not ct6;
				cnt6<='0';
			else
				cnt6<=not cnt6;
			end if;
		end if;
	end process;
	
	jzclk<=ct5;
	sxout<=ct4;
		
--  20ms:tset=1,tctrl=1
--	20us:tset=1,tctrl=0
--   2us:tset=0,tctrl=1
-- 100ns:tset=0,tctrl=0
	cho:process(tset,tctrl,ct0,ct2,ct3,sxin,sysclk,ct6)
	begin
		if tset='1' then
			ctrlclk<=ct0;
			if tctrl='1' then
				wrclk<=ct2;
			else
				wrclk<=ct0;
			end if;			
		else
			if tctrl='1' then
				wrclk<=ct3;
				ctrlclk<=ct3;
			else
				if kz='0' then
					wrclk<=sxin;
					ctrlclk<=sxin;
				else
					wrclk<=sysclk;
					ctrlclk<=ct6;
				end if;
			end if;
		end if;
	end process;
	
	ctrlnclk<=not ctrlclk;
			
	sx:process(sxin)
	begin
		if rising_edge(sxin) then
			if sxc="1001" then
				sxfk<=not sxfk;
				sxc<="0000";
			else
				sxc<=sxc+1;
			end if;
		end if;
	end process;
	sxfko<=sxfk;
			
--chufa kongzhi
--signal write
--save ctrl
	wr:process(wrclk)
	begin
	if	rising_edge(wrclk) then
		if dccf='1' then
				if cc='1' then
					wctrl1<='0';
					wdc1<=chf;
				else
					if	wctrl1='0' then
					wdc1<=chf;
						if chf='1' then
							wctrl1<='1';
						end if;
					else
						wdc1<='0';
					end if;
				end if;
			wdc<=chf;
			wctrl<='0';
		else
			if  wctrl='0' then
				wdc<=chf;
				if	chf='1' then
					wctrl<='1';
				end if;
			else
				wdc<='0';
			end if;
		end if;
		if	wadd="11111111" then
			if wdc='1' then
				wadd<="00000000";
			end if;
			wable<='0';
		else
			wable<='1';
			wadd<=wadd+1;
		end if;
		if	wadd1="11111111" then
			if wdc1='1' then
				wadd1<="00000000";
			end if;
			wable1<='0';
		else
			wable1<='1';
			wadd1<=wadd1+1;
		end if;
	end	if;
	end process;

--signal read
	rd:process(rdclk)
	begin
	if	rising_edge(rdclk) then
		radd<=radd+1;
		end if;
	end process;
	
	rdadd<=radd;
	
--display ctrl
	disp:process(xs,dout,dout1)
	begin
	if	xs='1' then
		do<=dout;
	else
		do<=dout1;
	end if;
	end process;
	
--dual channel ram ctrl
       process(wrclk)
       begin
              if wrclk'event and wrclk = '1' then
                     if wable = '1' then
                            dualram(conv_integer(wadd)) <= din;
                     end if;
              end if;
       end process;
   
       process(rdclk)
       begin
              if rdclk'event and rdclk = '1' then
                            dout <= dualram(conv_integer(radd));
              end if;
       end process;

       process(wrclk)
       begin
              if wrclk'event and wrclk = '1' then
                     if wable1 = '1' then
                            dualram1(conv_integer(wadd1)) <= din;
                     end if;
              end if;
       end process;
   
       process(rdclk)
       begin
              if rdclk'event and rdclk = '1' then
                            dout1 <= dualram1(conv_integer(radd));
              end if;
       end process;

end sbq;