📄 pyzc2.lst
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; Code Size : 46 Parameter Count:
; Stack Size: Parameter Size :
; OReg Size : Stack Depth : 18
212
213 void init_serial()
214 {
0186 init_serial:
215 1
216 1 /*
217 1 * Serial port configuration:
218 1 * serial mode = 1
219 1 * even parity = disabled
22 1 * serial receive = enabled
221 1 * serial transmit = enabled
222 1 */
223 1
224 1 _SetSFR_bit (ioc1, TXD_ENABLE_BIT);
0186 B10F00 E ldb wsr,#0FH
0189 B00000 E ldb tmpreg,ioc1
018C 912000 R orb tmpreg,#2
018F 1101 R clrb tmpreg+1
0191 1100 E clrb wsr
0193 B00000 E ldb ioc1,tmpreg
225 1 _WriteSFR (sp_con, 0x9);
0196 1100 E clrb wsr
0198 B10900 E ldb sp_con,#9
226 1
C196 Compiler pyzc2 13-Dec-106 22:07:20 Page 9
Assembly Listing of Object Code
227 1 /*
228 1 * Baud Rate = 0
229 1 */
23 1
231 1 _WriteSFR (baud_rate, 0x70);
019B 1100 E clrb wsr
019D B17000 E ldb baud_rate,#7
232 1 _WriteSFR (baud_rate, 0x82);
01A0 1100 E clrb wsr
01A2 B18200 E ldb baud_rate,#82H
233 1
234 1 /*
235 1 * Interrupts:
236 1 * transmit interrupt = disabled
237 1 * receive interrupt = disabled
238 1 * serial interrupt = enabled
239 1 */
24 1
241 1 _SetSFR_bit (int_mask, SERIAL_INT);
01A5 2000 br @0024
01A7 @0024:
01A7 B00000 E ldb tmpreg,int_mask
01AA 914000 R orb tmpreg,#4
01AD 1101 R clrb tmpreg+1
01AF 2000 br @0025
01B1 @0025:
01B1 B00000 E ldb int_mask,tmpreg
242 1 _ClrSFR_bit (int_mask1, TXD_INTERRUPT);
01B4 2000 br @0026
01B6 @0026:
01B6 AC0000 E ldbze tmpreg,imask1
01B9 61FEFF00 R and tmpreg,#0FFFEH
01BD 2000 br @0027
01BF @0027:
01BF B00000 E ldb imask1,tmpreg
243 1 _ClrSFR_bit (int_mask1, RXD_INTERRUPT);
01C2 2000 br @0028
01C4 @0028:
01C4 AC0000 E ldbze tmpreg,imask1
01C7 61FDFF00 R and tmpreg,#0FFFDH
01CB 2000 br @0029
01CD @0029:
01CD B00000 E ldb imask1,tmpreg
244 1
245 1
246 1 end_rec_buff=0; /* initialize buffer pointers */
01D0 1105 R clrb end_rec_buff
247 1 begin_rec_buff=0;
01D2 1106 R clrb begin_rec_buff
248 1 end_trans_buff=0;
01D4 1104 R clrb end_trans_buff
249 1 begin_trans_buff=0;
01D6 1103 R clrb begin_trans_buff
25 1 sp_status_image = 0x20; /* Init for initial transmittion */
01D8 B12002 R ldb sp_status_image,#2
251 1 }
C196 Compiler pyzc2 13-Dec-106 22:07:20 Page 1 01DB F0 ret
; Function Statistics for: init_serial
; Code Size : 86 Parameter Count:
; Stack Size: Parameter Size :
; OReg Size : Stack Depth :
252
253 void init_timer1(void)
254 {
01DC init_timer1:
255 1 /*
256 1 * Timer 1 configuration:
257 1 * overflow detection = enabled
258 1 */
259 1
26 1 _SetSFR_bit (ioc1, T1OVF_DETECTION);
01DC B10F00 E ldb wsr,#0FH
01DF B00000 E ldb tmpreg,ioc1
01E2 910400 R orb tmpreg,#4
01E5 1101 R clrb tmpreg+1
01E7 1100 E clrb wsr
01E9 B00000 E ldb ioc1,tmpreg
261 1
262 1 /*
263 1 * timer overflow interrupt = enabled
264 1 */
265 1
266 1 _SetSFR_bit (int_mask, TOVF_INT_MSK);
01EC 2000 br @002D
01EE @002D:
01EE B00000 E ldb tmpreg,int_mask
01F1 910100 R orb tmpreg,#1
01F4 1101 R clrb tmpreg+1
01F6 2000 br @002E
01F8 @002E:
01F8 B00000 E ldb int_mask,tmpreg
267 1 }
01FB F0 ret
; Function Statistics for: init_timer1
; Code Size : 32 Parameter Count:
; Stack Size: Parameter Size :
; OReg Size : Stack Depth :
268
269 void init_pwm0(void)
27 {
01FC init_pwm0:
271 1 /*
272 1 * PWM0 configuration:
273 1 * prescaler mode = divide by 1
274 1 * PWM output = enabled
275 1 * PWM duty cycle = 50.00 %
276 1 *
277 1 * pwm0_control = 256 * (Duty Cycle) / 100
C196 Compiler pyzc2 13-Dec-106 22:07:20 Page 11
Assembly Listing of Object Code
278 1 */
279 1
28 1 _ClrSFR_bit (ioc2, PWM_PRESCALE);
01FC B10F00 E ldb wsr,#0FH
01FF AC0000 E ldbze tmpreg,ioc2
0202 61FBFF00 R and tmpreg,#0FFFBH
0206 1100 E clrb wsr
0208 B00000 E ldb ioc2,tmpreg
281 1 _WriteSFR (pwm0_control, 0x80);
020B 1100 E clrb wsr
020D B18000 E ldb pwm_control,#8
282 1 _SetSFR_bit (ioc1, PWM0_ENABLE);
0210 B10F00 E ldb wsr,#0FH
0213 B00000 E ldb tmpreg,ioc1
0216 910100 R orb tmpreg,#1
0219 1101 R clrb tmpreg+1
021B 1100 E clrb wsr
021D B00000 E ldb ioc1,tmpreg
283 1 }
0220 F0 ret
; Function Statistics for: init_pwm0
; Code Size : 37 Parameter Count:
; Stack Size: Parameter Size :
; OReg Size : Stack Depth :
284
285 void init_hso1_5(void)
286 {
0221 init_hso1_5:
287 1 /*
288 1 * HSO 5 module initialization:
289 1 * HSO5 output = enabled
29 1 * cam locking = disabled
291 1 * clear cam = no
292 1 */
293 1
294 1 _SetSFR_bit (ioc1, HSO4_PIN_ENABLE);
0221 B10F00 E ldb wsr,#0FH
0224 B00000 E ldb tmpreg,ioc1
0227 911000 R orb tmpreg,#1
022A 1101 R clrb tmpreg+1
022C 1100 E clrb wsr
022E B00000 E ldb ioc1,tmpreg
295 1 _SetSFR_bit (ioc1, HSO5_PIN_ENABLE);
0231 B10F00 E ldb wsr,#0FH
0234 B00000 E ldb tmpreg,ioc1
0237 914000 R orb tmpreg,#4
023A 1101 R clrb tmpreg+1
023C 1100 E clrb wsr
023E B00000 E ldb ioc1,tmpreg
296 1 _ClrSFR_bit (ioc2, CAM_LOCK_BIT);
0241 B10F00 E ldb wsr,#0FH
0244 AC0000 E ldbze tmpreg,ioc2
0247 61BFFF00 R and tmpreg,#0FFBFH
024B 1100 E clrb wsr
C196 Compiler pyzc2 13-Dec-106 22:07:20 Page 12
Assembly Listing of Object Code
024D B00000 E ldb ioc2,tmpreg
297 1 _ClrSFR_bit (ioc2, CLEAR_CAM_BIT);
0250 B10F00 E ldb wsr,#0FH
0253 AC0000 E ldbze tmpreg,ioc2
0256 617FFF00 R and tmpreg,#0FF7FH
025A 1100 E clrb wsr
025C B00000 E ldb ioc2,tmpreg
298 1
299 1 /*
3 1 * Interrupts:
3 1 * HSO interrupt = disabled
3 1 * software timer int = disabled
3 1 */
3 1
3 1 _ClrSFR_bit (int_mask, HSO_INT);
025F 2000 br @003E
0261 @003E:
0261 AC0000 E ldbze tmpreg,int_mask
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