📄 wuxicar.lst
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01A0 981C00 cmpb R0,Tmp0
01A3 DF03 be @001E
236 2 {
237 3 ; /* User code for overrun error */
238 3 clrbit(sp_status_image, OE_BIT);
01A5 71FB02 R andb sp_status_image,#0FBH
01A8 @001E:
01A8 @001A:
239 3 }
24 2 }
241 1 clrbit(sp_status_image,RI_BIT); /* clear RI bit in status_image. */
01A8 71BF02 R andb sp_status_image,#0BFH
242 1 }
01AB CC00 R pop ?OVRBASE
01AD F0 ret
; Function Statistics for: receive
; Code Size : 2 Parameter Count:
; Stack Size: Parameter Size :
; OReg Size : 1 Stack Depth : 4
243
244 /* The seperate txd and rxd interrupts can more efficiently process
245 the interrupts than the generic serial interrupt as this one
246 does.
247 */
248
249 void serial_isr(void)
25 {
01AE serial_isr:
01AE F2 pushf
01AF C81C push Tmp0
01B1 C81E push Tmp2
01B3 C820 push Tmp4
01B5 C822 push Tmp6
251 1 sp_status_image |= sp_stat; /* image sp_stat into status_image */
01B7 900002 E orb sp_status_image,sp_stat
252 1
253 1 if(checkbit(sp_status_image, RI_BIT))
01BA 5140021C R andb Tmp0,sp_status_image,#4
01BE 981C00 cmpb R0,Tmp0
01C1 DF04 be @002
254 1 receive();
01C3 2F1A call receive
255 1 else if(checkbit(sp_status_image, TI_BIT))
01C5 200B br @0021
01C7 @002:
01C7 5120021C R andb Tmp0,sp_status_image,#2
01CB 981C00 cmpb R0,Tmp0
01CE DF02 be @0022
C196 Compiler wuxicar 30-May-107 11:11:06 Page 1 256 1 transmit();
01D0 2E93 call transmit
01D2 @0022:
01D2 @0021:
257 1 }
01D2 CC22 pop Tmp6
01D4 CC20 pop Tmp4
01D6 CC1E pop Tmp2
01D8 CC1C pop Tmp0
01DA F3 popf
01DB F0 ret
; Function Statistics for: serial_isr
; Code Size : 46 Parameter Count:
; Stack Size: Parameter Size :
; OReg Size : Stack Depth : 18
258
259 void init_serial()
26 {
01DC init_serial:
261 1
262 1 /*
263 1 * Serial port configuration:
264 1 * serial mode = 1
265 1 * even parity = disabled
266 1 * serial receive = enabled
267 1 * serial transmit = enabled
268 1 */
269 1
27 1 _SetSFR_bit (ioc1, TXD_ENABLE_BIT);
01DC B10F00 E ldb wsr,#0FH
01DF B00000 E ldb tmpreg,ioc1
01E2 912000 R orb tmpreg,#2
01E5 1101 R clrb tmpreg+1
01E7 1100 E clrb wsr
01E9 B00000 E ldb ioc1,tmpreg
271 1 _WriteSFR (sp_con, 0x9);
01EC 1100 E clrb wsr
01EE B10900 E ldb sp_con,#9
272 1
273 1 /*
274 1 * Baud Rate = 0
275 1 */
276 1
277 1 _WriteSFR (baud_rate, 0x70);
01F1 1100 E clrb wsr
01F3 B17000 E ldb baud_rate,#7
278 1 _WriteSFR (baud_rate, 0x82);
01F6 1100 E clrb wsr
01F8 B18200 E ldb baud_rate,#82H
279 1
28 1 /*
281 1 * Interrupts:
282 1 * transmit interrupt = disabled
283 1 * receive interrupt = disabled
C196 Compiler wuxicar 30-May-107 11:11:06 Page 11
Assembly Listing of Object Code
284 1 * serial interrupt = enabled
285 1 */
286 1
287 1 _SetSFR_bit (int_mask, SERIAL_INT);
01FB 2000 br @0029
01FD @0029:
01FD B00000 E ldb tmpreg,int_mask
0200 914000 R orb tmpreg,#4
0203 1101 R clrb tmpreg+1
0205 2000 br @002A
0207 @002A:
0207 B00000 E ldb int_mask,tmpreg
288 1 _ClrSFR_bit (int_mask1, TXD_INTERRUPT);
020A 2000 br @002B
020C @002B:
020C AC0000 E ldbze tmpreg,imask1
020F 61FEFF00 R and tmpreg,#0FFFEH
0213 2000 br @002C
0215 @002C:
0215 B00000 E ldb imask1,tmpreg
289 1 _ClrSFR_bit (int_mask1, RXD_INTERRUPT);
0218 2000 br @002D
021A @002D:
021A AC0000 E ldbze tmpreg,imask1
021D 61FDFF00 R and tmpreg,#0FFFDH
0221 2000 br @002E
0223 @002E:
0223 B00000 E ldb imask1,tmpreg
29 1
291 1
292 1 end_rec_buff=0; /* initialize buffer pointers */
0226 1105 R clrb end_rec_buff
293 1 begin_rec_buff=0;
0228 1106 R clrb begin_rec_buff
294 1 end_trans_buff=0;
022A 1104 R clrb end_trans_buff
295 1 begin_trans_buff=0;
022C 1103 R clrb begin_trans_buff
296 1 sp_status_image = 0x20; /* Init for initial transmittion */
022E B12002 R ldb sp_status_image,#2
297 1 }
0231 F0 ret
; Function Statistics for: init_serial
; Code Size : 86 Parameter Count:
; Stack Size: Parameter Size :
; OReg Size : Stack Depth :
298
299 void init_timer1(void)
3 {
0232 init_timer1:
3 1 /*
3 1 * Timer 1 configuration:
3 1 * overflow detection = enabled
3 1 */
C196 Compiler wuxicar 30-May-107 11:11:06 Page 12
Assembly Listing of Object Code
3 1
3 1 _SetSFR_bit (ioc1, T1OVF_DETECTION);
0232 B10F00 E ldb wsr,#0FH
0235 B00000 E ldb tmpreg,ioc1
0238 910400 R orb tmpreg,#4
023B 1101 R clrb tmpreg+1
023D 1100 E clrb wsr
023F B00000 E ldb ioc1,tmpreg
3 1
3 1 /*
3 1 * timer overflow interrupt = enabled
31 1 */
311 1
312 1 _SetSFR_bit (int_mask, TOVF_INT_MSK);
0242 2000 br @0032
0244 @0032:
0244 B00000 E ldb tmpreg,int_mask
0247 910100 R orb tmpreg,#1
024A 1101 R clrb tmpreg+1
024C 2000 br @0033
024E @0033:
024E B00000 E ldb int_mask,tmpreg
313 1 }
0251 F0 ret
; Function Statistics for: init_timer1
; Code Size : 32 Parameter Count:
; Stack Size: Parameter Size :
; OReg Size : Stack Depth :
314
315 void init_pwm0(void)
316 {
0252 init_pwm0:
317 1 /*
318 1 * PWM0 configuration:
319 1 * prescaler mode = divide by 1
32 1 * PWM output = enabled
321 1 * PWM duty cycle = 50.00 %
322 1 *
323 1 * pwm0_control = 256 * (Duty Cycle) / 100
324 1 */
325 1
326 1 _ClrSFR_bit (ioc2, PWM_PRESCALE);
0252 B10F00 E ldb wsr,#0FH
0255 AC0000 E ldbze tmpreg,ioc2
0258 61FBFF00 R and tmpreg,#0FFFBH
025C 1100 E clrb wsr
025E B00000 E ldb ioc2,tmpreg
327 1 _WriteSFR (pwm0_control, 0x80);
0261 1100 E clrb wsr
0263 B18000 E ldb pwm_control,#8
328 1 _SetSFR_bit (ioc1, PWM0_ENABLE);
0266 B10F00 E ldb wsr,#0FH
0269 B00000 E ldb tmpreg,ioc1
026C 910100 R orb tmpreg,#1
C196 Compiler wuxicar 30-May-107 11:11:06 Page 13
Assembly Listing of Object Code
026F 1101 R clrb tmpreg+1
0271 1100 E clrb wsr
0273 B00000 E ldb ioc1,tmpreg
329 1 }
0276 F0 ret
; Function Statistics for: init_pwm0
; Code Size : 37 Parameter Count:
; Stack Size: Parameter Size :
; OReg Size : Stack Depth :
33
331 void init_hso1_5(void)
332 {
0277 init_hso1_5:
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