register.h

基于ADSP-BF535 USB驱动应用程序

#define EVT3_REG          (*(PVUL)(EVT3))  // Event Vector 3 ESR Address
#define EVT4_REG          (*(PVUL)(EVT4))  // Event Vector 4 ESR Address
#define EVT5_REG          (*(PVUL)(EVT5))  // Event Vector 5 ESR Address
#define EVT6_REG          (*(PVUL)(EVT6))  // Event Vector 6 ESR Address
#define EVT7_REG          (*(PVUL)(EVT7))  // Event Vector 7 ESR Address
#define EVT8_REG          (*(PVUL)(EVT8))  // Event Vector 8 ESR Address
#define EVT9_REG          (*(PVUL)(EVT9))  // Event Vector 9 ESR Address
#define EVT10_REG         (*(PVUL)(EVT10)) // Event Vector 10 ESR Address
#define EVT11_REG         (*(PVUL)(EVT11)) // Event Vector 11 ESR Address
#define EVT12_REG         (*(PVUL)(EVT12)) // Event Vector 12 ESR Address
#define EVT13_REG         (*(PVUL)(EVT13)) // Event Vector 13 ESR Address
#define EVT14_REG         (*(PVUL)(EVT14)) // Event Vector 14 ESR Address
#define EVT15_REG         (*(PVUL)(EVT15)) // Event Vector 15 ESR Address
#define EVT_OVERRIDE_REG  (*(PVUL)(EVT_OVERRIDE))// Event Vector Table Override Register
#define IMASK_REG         (*(PVUL)(IMASK)) // Interrupt Mask Register
#define IPEND_REG         (*(PVUL)(IPEND)) // Interrupt Pending Register
#define ILAT_REG          (*(PVUL)(ILAT))  // Interrupt Latch Register

/*==================================================================================
// Core Timer Registers
====================================================================================*/
#define TCNTL_REG    (*(PVUL)(TCNTL))    // Core Timer Control Register
#define TPERIOD_REG  (*(PVUL)(TPERIOD))  // Core Timer Period Register
#define TSCALE_REG   (*(PVUL)(TSCALE))   // Core Timer Scale Register
#define TCOUNT_REG   (*(PVUL)(TCOUNT))   // Core Timer Count Register

/*==================================================================================
// Debug/MP/Emulation Registers
====================================================================================*/
#define DSPID_REG    (*(PVUL)(DSPID))    // DSP Processor ID Register for MP implementations
#define DBGCTL_REG   (*(PVUL)(DBGCTL))   // Debug Control Register
#define DBGSTAT_REG  (*(PVUL)(DBGSTAT))  // Debug Status Register
#define EMUDAT_REG   (*(PVUL)(EMUDAT))   // Emulator Data Register

/*==================================================================================
// Trace Buffer Registers
====================================================================================*/
#define TBUFCTL_REG   (*(PVUL)(TBUFCTL))   // Trace Buffer Control Register
#define TBUFSTAT_REG  (*(PVUL)(TBUFSTAT))  // Trace Buffer Status Register
#define TBUF_REG      (*(PVUL)(TBUF))      // Trace Buffer

/*==================================================================================
// Watch Point Control Registers
====================================================================================*/
#define WPIACTL_REG    (*(PVUL)(WPIACTL))  // Instruction Watch Point Control Register
#define WPIA0_REG      (*(PVUL)(WPIA0))    // Instruction Watch Point Address 0
#define WPIA1_REG      (*(PVUL)(WPIA1))    // Instruction Watch Point Address 1
#define WPIA2_REG      (*(PVUL)(WPIA2))    // Instruction Watch Point Address 2
#define WPIA3_REG      (*(PVUL)(WPIA3))    // Instruction Watch Point Address 3
#define WPIA4_REG      (*(PVUL)(WPIA4))    // Instruction Watch Point Address 4
#define WPIA5_REG      (*(PVUL)(WPIA5))    // Instruction Watch Point Address 5
#define WPIACNT0_REG   (*(PVUL)(WPIACNT0)) // Instruction Watch Point Counter 0
#define WPIACNT1_REG   (*(PVUL)(WPIACNT1)) // Instruction Watch Point Counter 1
#define WPIACNT2_REG   (*(PVUL)(WPIACNT2)) // Instruction Watch Point Counter 2
#define WPIACNT3_REG   (*(PVUL)(WPIACNT3)) // Instruction Watch Point Counter 3
#define WPIACNT4_REG   (*(PVUL)(WPIACNT4)) // Instruction Watch Point Counter 4
#define WPIACNT5_REG   (*(PVUL)(WPIACNT5)) // Instruction Watch Point Counter 5
#define WPDACTL_REG    (*(PVUL)(WPDACTL))  // Data Watch Point Control Register
#define WPDA0_REG      (*(PVUL)(WPDA0))    // Data Watch Point Address 0
#define WPDA1_REG      (*(PVUL)(WPDA1))    // Data Watch Point Address 1
#define WPDACNT0_REG   (*(PVUL)(WPDACNT0)) // Data Watch Point Counter 0
#define WPDACNT1_REG   (*(PVUL)(WPDACNT1)) // Data Watch Point Counter 1
#define WPSTAT_REG     (*(PVUL)(WPSTAT))   // Watch Point Status Register

/*==================================================================================
// Performance Monitor Registers
====================================================================================*/
#define PFCTL_REG     (*(PVUL)(PFCTL))    // Performance Monitor Control Register
#define PFCNTR0_REG   (*(PVUL)(PFCNTR0))  // Performance Monitor Counter Register 0
#define PFCNTR1_REG   (*(PVUL)(PFCNTR1))  // Performance Monitor Counter Register 1




//===============================================================================
/*
// setup the General purpose register first !
#define FIO_DIR_REG		(*(PVUS)(FIO_DIR))
#define FIO_FLAG_S_REG	(*(PVUS)(FIO_FLAG_S))
#define FIO_FLAG_C_REG	(*(PVUS)(FIO_FLAG_C))

// setup the timer register 
#define TPERIOD_REG (*(PVUL)(TPERIOD))
#define TSCALE_REG  (*(PVUL)(TSCALE))
#define TCOUNT_REG  (*(PVUL)(TCOUNT))
#define TCNTL_REG	(*(PVUL)(TCNTL))

// setup interrupt mask register
#define IMASK_REG	(*(PVUL)(IMASK))
#define IPEND_REG	(*(PVUL)(IPEND))
#define ILAT_REG	(*(PVUL)(ILAT))
*/


//------------------------------------------------------------------------------
// Flag pins 
//------------------------------------------------------------------------------

#define bPF0		0
#define bPF1		1
#define bPF2		2
#define bPF3		3
#define bPF4		4
#define bPF5		5
#define bPF6		6
#define bPF7		7
#define bPF8		8
#define bPF9		9
#define bPF10		10
#define bPF11		11
#define bPF12		12
#define bPF13		13
#define bPF14		14


//------------------------------------------------------------------------------
// SPORTx 
//------------------------------------------------------------------------------

// SPORTx_TX_CONFIG 

#define	bTxTSPEN 0
#define	bTxICLK  1
#define	bTxDTYPE 2
#define	bTxSENDN 4
#define	bTxSLEN  5
#define	bTxITFS  9
#define	bTxTFSR  10
#define	bTxDITFS 11
#define	bTxLTFS  12
#define	bTxLATFS 13
#define	bTxCKFE  14
#define	bTxICLKD 15

//..............................................................................

// SPORTx_RX_CONFIG 

#define	bRxRSPEN 0
#define	bRxICLK  1
#define	bRxDTYPE 2
#define	bRxSENDN 4
#define	bRxSLEN  5
#define	bRxIRFS  9
#define	bRxRFSR  10
#define	bRxLRFS  12
#define	bRxLARFS 13
#define	bRxCKFE  14
#define	bRxICLKD 15

//..............................................................................
// SPORTx_STAT
#define bROVF 0
#define bRXS 1
#define bTXS 2
#define bTUVF 3
#define bCHNL 4

//..............................................................................
// SPORTx_IRQSTAT_RX

#define bRxCOMPL  0 
#define bRxERR    1
#define bRxBUSERR 2

// SPORTx_IRQSTAT_TX

#define bTxCOMPL  0 
#define bTxERR    1
#define bTxBUSERR 2
 
// SPORTx_MCMC1

#define bMCM   0
#define bMFD   1
#define bWSIZE 5
#define bWOFF  9

// SPORTx_MCMC2

#define bMCCRM   0
#define bMCDTXPE 2
#define bMCDRXPE 3
#define bMCOM    4
#define bMCFF    5
#define bFSDR    7

// SPORTx_CONFIG_DMA_TX

#define bTxDEN   0
#define bTxTRAN  1
#define bTxDCOME 2
#define bTxDSB0  3
#define bTxDAUTO 4
#define bTxFLSH  7
#define bTxDERE  8
#define bTxTUVF  9
#define bTxDSB1  12
#define bTxFS    12
#define bTxDS    14
#define bTxDOWN  15

#define kTxDAUTO   ZET(bTxDAUTO,1) 

// SPORTx_CONFIG_DMA_RX

#define bRxDEN   0
#define bRxTRAN  1
#define bRxDCOME 2
#define bRxDSB0  3
#define bRxDAUTO 4
#define bRxFLSH  7
#define bRxDERE  8
#define bRxROVF  9
#define bRxDSB1  12
#define bRxFS    12
#define bRxDS    14
#define bRxDOWN  15





#endif