📄 register.h
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====================================================================================*/
#define SPORT1_TX_CONFIG_REG (*(PVUS)(SPORT1_TX_CONFIG)) // SPORT1 Transmit Configuration Register
#define SPORT1_RX_CONFIG_REG (*(PVUS)(SPORT1_RX_CONFIG)) // SPORT1 Receive Configuration Register
#define SPORT1_TX_REG (*(PVUS)(SPORT1_TX)) // SPORT1 TX transmit Register
#define SPORT1_RX_REG (*(PVUS)(SPORT1_RX)) // SPORT1 RX Receive register
#define SPORT1_TSCLKDIV_REG (*(PVUS)(SPORT1_TSCLKDIV)) // SPORT1 Transmit Serial Clock Divider
#define SPORT1_RSCLKDIV_REG (*(PVUS)(SPORT1_RSCLKDIV)) // SPORT1 Receive Serial Clock Divider
#define SPORT1_TFSDIV_REG (*(PVUS)(SPORT1_TFSDIV)) // SPORT1 Transmit Frame Sync Divider
#define SPORT1_RFSDIV_REG (*(PVUS)(SPORT1_RFSDIV)) // SPORT1 Receive Frame Sync Divider
#define SPORT1_STAT_REG (*(PVUS)(SPORT1_STAT)) // SPORT1 Status Register
#define SPORT1_MTCS0_REG (*(PVUS)(SPORT1_MTCS0)) // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS1_REG (*(PVUS)(SPORT1_MTCS1)) // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS2_REG (*(PVUS)(SPORT1_MTCS2)) // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS3_REG (*(PVUS)(SPORT1_MTCS3)) // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS4_REG (*(PVUS)(SPORT1_MTCS4)) // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS5_REG (*(PVUS)(SPORT1_MTCS5)) // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS6_REG (*(PVUS)(SPORT1_MTCS6)) // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MTCS7_REG (*(PVUS)(SPORT1_MTCS7)) // SPORT1 Multi-Channel Transmit Select Register
#define SPORT1_MRCS0_REG (*(PVUS)(SPORT1_MRCS0)) // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS1_REG (*(PVUS)(SPORT1_MRCS1)) // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS2_REG (*(PVUS)(SPORT1_MRCS2)) // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS3_REG (*(PVUS)(SPORT1_MRCS3)) // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS4_REG (*(PVUS)(SPORT1_MRCS4)) // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS5_REG (*(PVUS)(SPORT1_MRCS5)) // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS6_REG (*(PVUS)(SPORT1_MRCS6)) // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MRCS7_REG (*(PVUS)(SPORT1_MRCS7)) // SPORT1 Multi-Channel Receive Select Register
#define SPORT1_MCMC1_REG (*(PVUS)(SPORT1_MCMC1)) // SPORT1 Multi-Channel Configuration Register 1
#define SPORT1_MCMC2_REG (*(PVUS)(SPORT1_MCMC2)) // SPORT1 Multi-Channel Configuration Register 2
#define SPORT1_CURR_PTR_RX_REG (*(PVUS)(SPORT1_CURR_PTR_RX)) // SPORT1 -RCV DMA Current Pointer
#define SPORT1_CONFIG_DMA_RX_REG (*(PVUS)(SPORT1_CONFIG_DMA_RX)) // SPORT1 -RCV DMA Configuration
#define SPORT1_START_ADDR_HI_RX_REG (*(PVUS)(SPORT1_START_ADDR_HI_RX))// SPORT1 -RCV DMA Start Page
#define SPORT1_START_ADDR_LO_RX_REG (*(PVUS)(SPORT1_START_ADDR_LO_RX))// SPORT1 -RCV DMA Start Address
#define SPORT1_COUNT_RX_REG (*(PVUS)(SPORT1_COUNT_RX)) // SPORT1 -RCV DMA Count
#define SPORT1_NEXT_DESCR_RX_REG (*(PVUS)(SPORT1_NEXT_DESCR_RX)) // SPORT1 -RCV DMA Next Descriptor Pointer
#define SPORT1_DESCR_RDY_RX_REG (*(PVUS)(SPORT1_DESCR_RDY_RX)) // SPORT1 -RCV DMA Descriptor Ready
#define SPORT1_IRQSTAT_RX_REG (*(PVUS)(SPORT1_IRQSTAT_RX)) // SPORT1 -RCV DMA Interrupt Register
#define SPORT1_CURR_PTR_TX_REG (*(PVUS)(SPORT1_CURR_PTR_TX)) // SPORT1 -XMT DMA Current Pointer
#define SPORT1_CONFIG_DMA_TX_REG (*(PVUS)(SPORT1_CONFIG_DMA_TX)) // SPORT1 -XMT DMA Configuration
#define SPORT1_START_ADDR_HI_TX_REG (*(PVUS)(SPORT1_START_ADDR_HI_TX))// SPORT1 -XMT DMA Start Page
#define SPORT1_START_ADDR_LO_TX_REG (*(PVUS)(SPORT1_START_ADDR_LO_TX))// SPORT1 -XMT DMA Start Address
#define SPORT1_COUNT_TX_REG (*(PVUS)(SPORT1_COUNT_TX)) // SPORT1 -XMT DMA Count
#define SPORT1_NEXT_DESCR_TX_REG (*(PVUS)(SPORT1_NEXT_DESCR_TX)) // SPORT1 -XMT DMA Next Descriptor Pointer
#define SPORT1_DESCR_RDY_TX_REG (*(PVUS)(SPORT1_DESCR_RDY_TX)) // SPORT1 -XMT DMA Descriptor Ready
#define SPORT1_IRQSTAT_TX_REG (*(PVUS)(SPORT1_IRQSTAT_TX)) // SPORT1 -XMT DMA Interrupt Register
/*==================================================================================
// SPI 0 Controller (0xFFC0 3000-0xFFC0 33FF)
====================================================================================*/
#define SPI0_CTL_REG (*(PVUS)(SPI0_CTL)) // SPI0 Control Register
#define SPI0_FLG_REG (*(PVUS)(SPI0_FLG)) // SPI0 Flag register
#define SPI0_ST_REG (*(PVUS)(SPI0_ST)) // SPI0 Status register
#define SPI0_TDBR_REG (*(PVUS)(SPI0_TDBR)) // SPI0 Transmit Data Buffer Register
#define SPI0_RDBR_REG (*(PVUS)(SPI0_RDBR)) // SPI0 Receive Data Buffer Register
#define SPI0_BAUD_REG (*(PVUS)(SPI0_BAUD)) // SPI0 Baud rate Register
#define SPI0_SHADOW_REG (*(PVUS)(SPI0_SHADOW))
#define SPI0_CURR_PTR_REG (*(PVUS)(SPI0_CURR_PTR)) // SPI0 -DMA Current Pointer register
#define SPI0_CONFIG_REG (*(PVUS)(SPI0_CONFIG)) // SPI0 -DMA Configuration register
#define SPI0_START_ADDR_HI_REG (*(PVUS)(SPI0_START_ADDR_HI)) // SPI0 -DMA Start Page register
#define SPI0_START_ADDR_LO_REG (*(PVUS)(SPI0_START_ADDR_LO)) // SPI0 -DMA Start Address register
#define SPI0_COUNT_REG (*(PVUS)(SPI0_COUNT)) // SPI0 -DMA Count register
#define SPI0_NEXT_DESCR_REG (*(PVUS)(SPI0_NEXT_DESCR))// SPI0 -DMA Next Descriptor Pointer
#define SPI0_DESCR_RDY_REG (*(PVUS)(SPI0_DESCR_RDY)) // SPI0 -DMA Descriptor Ready
#define SPI0_DMA_INT_REG (*(PVUS)(SPI0_DMA_INT)) // SPI0 -DMA Interrupt register
/*==================================================================================
// SPI 1 Controller (0xFFC0 3400-0xFFC0 37FF)
====================================================================================*/
#define SPI1_CTL_REG (*(PVUS)(SPI1_CTL)) // SPI1 Control Register
#define SPI1_FLG_REG (*(PVUS)(SPI1_FLG)) // SPI1 Flag register
#define SPI1_ST_REG (*(PVUS)(SPI1_ST)) // SPI1 Status register
#define SPI1_TDBR_REG (*(PVUS)(SPI1_TDBR)) // SPI1 Transmit Data Buffer Register
#define SPI1_RDBR_REG (*(PVUS)(SPI1_RDBR)) // SPI1 Receive Data Buffer Register
#define SPI1_BAUD_REG (*(PVUS)(SPI1_BAUD)) // SPI1 Baud rate Register
#define SPI1_SHADOW_REG (*(PVUS)(SPI1_SHADOW))
#define SPI1_CURR_PTR_REG (*(PVUS)(SPI1_CURR_PTR)) // SPI1 -DMA Current Pointer register
#define SPI1_CONFIG_REG (*(PVUS)(SPI1_CONFIG)) // SPI1 -DMA Configuration register
#define SPI1_START_ADDR_HI_REG (*(PVUS)(SPI1_START_ADDR_HI)) // SPI1 -DMA Start Page register
#define SPI1_START_ADDR_LO_REG (*(PVUS)(SPI1_START_ADDR_LO)) // SPI1 -DMA Start Address register
#define SPI1_COUNT_REG (*(PVUS)(SPI1_COUNT)) // SPI1 -DMA Count register
#define SPI1_NEXT_DESCR_REG (*(PVUS)(SPI1_NEXT_DESCR))// SPI1 -DMA Next Descriptor Pointer
#define SPI1_DESCR_RDY_REG (*(PVUS)(SPI1_DESCR_RDY)) // SPI1 -DMA Descriptor Ready
#define SPI1_DMA_INT_REG (*(PVUS)(SPI1_DMA_INT)) // SPI1 -DMA Interrupt register
/*==================================================================================
// Memory DMA Controller (0xFFC0 3800-0xFFC0 3BFF)
====================================================================================*/
#define MDW_DCP_REG (*(PVUS)(MDW_DCP)) // Current Pointer - Write Channel
#define MDW_DCFG_REG (*(PVUS)(MDW_DCFG)) // DMA Configuration - Write Channel
#define MDW_DSAH_REG (*(PVUS)(MDW_DSAH)) // Start Address Hi - Write Channel
#define MDW_DSAL_REG (*(PVUS)(MDW_DSAL)) // Start Address Lo - Write Channel
#define MDW_DCT_REG (*(PVUS)(MDW_DCT)) // DMA Count - Write Channel
#define MDW_DND_REG (*(PVUS)(MDW_DND)) // Next Descriptor Pointer - Write Channel
#define MDW_DDR_REG (*(PVUS)(MDW_DDR)) // Descriptor Ready - Write Channel
#define MDW_DI_REG (*(PVUS)(MDW_DI)) // DMA Interrupt - Write Channel
#define MDR_DCP_REG (*(PVUS)(MDR_DCP)) // Current Pointer - Read Channel
#define MDR_DCFG_REG (*(PVUS)(MDR_DCFG)) // DMA Configuration - Read Channel
#define MDR_DSAH_REG (*(PVUS)(MDR_DSAH)) // Start Address Hi - Read Channel
#define MDR_DSAL_REG (*(PVUS)(MDR_DSAL)) // Start Address Lo - Read Channel
#define MDR_DCT_REG (*(PVUS)(MDR_DCT)) // DMA Count - Read Channel
#define MDR_DND_REG (*(PVUS)(MDR_DND)) // Next Descriptor Pointer - Read Channel
#define MDR_DDR_REG (*(PVUS)(MDR_DDR)) // Descriptor Ready - Read Channel
#define MDR_DI_REG (*(PVUS)(MDR_DI)) // DMA Interrupt - Read Channel
/*==================================================================================
// Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF)
====================================================================================*/
#define EBIU_AMGCTL_REG (*(PVUS)(EBIU_AMGCTL)) // Asynchronous Memory Global Control Register
#define EBIU_AMBCTL0_REG (*(PVUL)(EBIU_AMBCTL0)) // Asynchronous Memory Bank Control Register 0
#define EBIU_AMBCTL1_REG (*(PVUL)(EBIU_AMBCTL1)) // Asynchronous Memory Bank Control Register 1
/*==================================================================================
// PCI Bridge PAB Registers (0xFFC0 4000-0xFFC0 43FF)
====================================================================================*/
#define PCI_CTL_REG (*(PVUL)(PCI_CTL)) // PCI Bridge Control
#define PCI_STAT_REG (*(PVUL)(PCI_STAT)) // PCI Bridge Status
#define PCI_ICTL_REG (*(PVUL)(PCI_ICTL)) // PCI Bridge Interrupt Control
#define PCI_MBAP_REG (*(PVUL)(PCI_MBAP)) // PCI Memory Space Base Address Pointer [31:27]
#define PCI_IBAP_REG (*(PVUL)(PCI_IBAP)) // PCI IO Space Base Address Pointer
#define PCI_CBAP_REG (*(PVUL)(PCI_CBAP)) // PCI Config Space Base Address Port
#define PCI_TMBAP_REG (*(PVUL)(PCI_TMBAP)) // PCI to 21535 Memory Base Address Pointer
#define PCI_TIBAP_REG (*(PVUL)(PCI_TIBAP)) // PCI to 21535 IO Base Address Pointer
/*==================================================================================
// PCI Bridge External Access Bus Registers (0xEEFF FF00-0xEEFF FFFF)
====================================================================================*/
#define PCI_DMBARM_REG (*(PVUL)(PCI_DMBARM)) // PCI Device Memory Bar Mask
#define PCI_DIBARM_REG (*(PVUL)(PCI_DIBARM)) // PCI Device IO Bar Mask
#define PCI_CFG_DIC_REG (*(PVUL)(PCI_CFG_DIC)) // PCI Config Device ID
#define PCI_CFG_VIC_REG (*(PVUL)(PCI_CFG_VIC)) // PCI Config Vendor ID
#define PCI_CFG_STAT_REG (*(PVUL)(PCI_CFG_STAT)) // PCI Config Status (Read-only)
#define PCI_CFG_CMD_REG (*(PVUL)(PCI_CFG_CMD)) // PCI Config Command
#define PCI_CFG_CC_REG (*(PVUL)(PCI_CFG_CC)) // PCI Config Class Code
#define PCI_CFG_RID_REG (*(PVUL)(PCI_CFG_RID)) // PCI Config Revision ID
#define PCI_CFG_BIST_REG (*(PVUL)(PCI_CFG_BIST)) // PCI Config BIST
#define PCI_CFG_HT_REG (*(PVUL)(PCI_CFG_HT)) // PCI Config Header Type
#define PCI_CFG_MLT_REG (*(PVUL)(PCI_CFG_MLT)) // PCI Config Memory Latency Timer
#define PCI_CFG_CLS_REG (*(PVUL)(PCI_CFG_CLS)) // PCI Config Cache Line Size
#define PCI_CFG_MBAR_REG (*(PVUL)(PCI_CFG_MBAR)) // PCI Config Memory Base Address Register
#define PCI_CFG_IBAR_REG (*(PVUL)(PCI_CFG_IBAR)) // PCI Config IO Base Address Register
#define PCI_CFG_SID_REG (*(PVUL)(PCI_CFG_SID)) // PCI Config Sub-system ID
#define PCI_CFG_SVID_REG (*(PVUL)(PCI_CFG_SVID)) // PCI Config Sub-system Vendor ID
#define PCI_CFG_MAXL_REG (*(PVUL)(PCI_CFG_MAXL)) // PCI Config Maximum Latency Cycles
#define PCI_CFG_MING_REG (*(PVUL)(PCI_CFG_MING)) // PCI Config Minimum Grant Cycles
#define PCI_CFG_IP_REG (*(PVUL)(PCI_CFG_IP)) // PCI Config Interrupt Pin
#define PCI_CFG_IL_REG (*(PVUL)(PCI_CFG_IL)) // PCI Config Interrupt Line
#define PCI_HMCTL_REG (*(PVUL)(PCI_HMCTL)) // PCI Blocking BAR Host Mode Control
/*==================================================================================
// USB Registers (0xFFC0 4400 - 0xFFC0 47FF)
====================================================================================*/
#define USBD_ID_REG (*(PVUS)(USBD_ID)) // USB Device ID Register
#define USBD_FRM_REG (*(PVUS)(USBD_FRM)) // Current USB Frame Number
#define USBD_FRMAT_REG (*(PVUS)(USBD_FRMAT)) // Match value for USB frame number.
#define USBD_EPBUF_REG (*(PVUS)(USBD_EPBUF)) // Enables Download of Configuration Into UDC Core
#define USBD_STAT_REG (*(PVUS)(USBD_STAT)) // Returns USBD Module Status
#define USBD_CTRL_REG (*(PVUS)(USBD_CTRL)) // Allows Configuration and Control of USBD Module.
#define USBD_GINTR_REG (*(PVUS)(USBD_GINTR)) // Global Interrupt Register
#define USBD_GMASK_REG (*(PVUS)(USBD_GMASK)) // Global Interrupt Register Mask
#define USBD_DMACFG_REG (*(PVUS)(USBD_DMACFG)) // DMA Master Channel Configuration Register
#define USBD_DMABL_REG (*(PVUS)(USBD_DMABL)) // DMA Master Channel Base Address, Low
#define USBD_DMABH_REG (*(PVUS)(USBD_DMABH)) // DMA Master Channel Base Address, High
#define USBD_DMACT_REG (*(PVUS)(USBD_DMACT)) // DMA Master Channel Count Register
#define USBD_DMAIRQ_REG (*(PVUS)(USBD_DMAIRQ)) // DMA Master Channel DMA Count Register
#define USBD_INTR0_REG (*(PVUS)(USBD_INTR0)) // USB Endpoint 0 Interrupt Register
#define USBD_MASK0_REG (*(PVUS)(USBD_MASK0)) // USB Endpoint 0 Mask Register
#define USBD_EPCFG0_REG (*(PVUS)(USBD_EPCFG0)) // USB Endpoint 0 Control Register
#define USBD_EPADR0_REG (*(PVUS)(USBD_EPADR0)) // USB Endpoint 0 Address Offset Register
#define USBD_EPLEN0_REG (*(PVUS)(USBD_EPLEN0)) // USB Endpoint 0 Buffer Length Register
#define USBD_INTR1_REG (*(PVUS)(USBD_INTR1)) // USB Endpoint 1 Interrupt Register
#define USBD_MASK1_REG (*(PVUS)(USBD_MASK1)) // USB Endpoint 1 Mask Register
#define USBD_EPCFG1_REG (*(PVUS)(USBD_EPCFG1)) // USB Endpoint 1 Control Register
#define USBD_EPADR1_REG (*(PVUS)(USBD_EPADR1)) // USB Endpoint 1 Address Offset Register
#define USBD_EPLEN1_REG (*(PVUS)(USBD_EPLEN1)) // USB Endpoint 1 Buffer Length Register
#define USBD_INTR2_REG (*(PVUS)(USBD_INTR2)) // USB Endpoint 2 Interrupt Register
#define USBD_MASK2_REG (*(PVUS)(USBD_MASK2)) // USB Endpoint 2 Mask Register
#define USBD_EPCFG2_REG (*(PVUS)(USBD_EPCFG2)) // USB Endpoint 2 Control Register
#define USBD_EPADR2_REG (*(PVUS)(USBD_EPADR2)) // USB Endpoint 2 Address Offset Register
#define USBD_EPLEN2_REG (*(PVUS)(USBD_EPLEN2)) // USB Endpoint 2 Buffer Length Register
#define USBD_INTR3_REG (*(PVUS)(USBD_INTR3)) // USB Endpoint 3 Interrupt Register
#define USBD_MASK3_REG (*(PVUS)(USBD_MASK3)) // USB Endpoint 3 Mask Register
#define USBD_EPCFG3_REG (*(PVUS)(USBD_EPCFG3)) // USB Endpoint 3 Control Register
#define USBD_EPADR3_REG (*(PVUS)(USBD_EPADR3)) // USB Endpoint 3 Address Offset Register
#define USBD_EPLEN3_REG (*(PVUS)(USBD_EPLEN3)) // USB Endpoint 3 Buffer Length Register
#define USBD_INTR4_REG (*(PVUS)(USBD_INTR4)) // USB Endpoint 4 Interrupt Register
#define USBD_MASK4_REG (*(PVUS)(USBD_MASK4)) // USB Endpoint 4 Mask Register
#define USBD_EPCFG4_REG (*(PVUS)(USBD_EPCFG4)) // USB Endpoint 4 Control Register
#define USBD_EPADR4_REG (*(PVUS)(USBD_EPADR4)) // USB Endpoint 4 Address Offset Register
#define USBD_EPLEN4_REG (*(PVUS)(USBD_EPLEN4)) // USB Endpoint 4 Buffer Length Register
#define USBD_INTR5_REG (*(PVUS)(USBD_INTR5)) // USB Endpoint 5 Interrupt Register
#define USBD_MASK5_REG (*(PVUS)(USBD_MASK5)) // USB Endpoint 5 Mask Register
#define USBD_EPCFG5_REG (*(PVUS)(USBD_EPCFG5)) // USB Endpoint 5 Control Register
#define USBD_EPADR5_REG (*(PVUS)(USBD_EPADR5)) // USB Endpoint 5 Address Offset Register
#define USBD_EPLEN5_REG (*(PVUS)(USBD_EPLEN5)) // USB Endpoint 5 Buffer Length Register
#define USBD_INTR6_REG (*(PVUS)(USBD_INTR6)) // USB Endpoint 6 Interrupt Register
#define USBD_MASK6_REG (*(PVUS)(USBD_MASK6)) // USB Endpoint 6 Mask Register
#define USBD_EPCFG6_REG (*(PVUS)(USBD_EPCFG6)) // USB Endpoint 6 Control Register
#define USBD_EPADR6_REG (*(PVUS)(USBD_EPADR6)) // USB Endpoint 6 Address Offset Register
#define USBD_EPLEN6_REG (*(PVUS)(USBD_EPLEN6)) // USB Endpoint 6 Buffer Length Register
#define USBD_INTR7_REG (*(PVUS)(USBD_INTR7)) // USB Endpoint 7 Interrupt Register
#define USBD_MASK7_REG (*(PVUS)(USBD_MASK7)) // USB Endpoint 7 Mask Register
#define USBD_EPCFG7_REG (*(PVUS)(USBD_EPCFG7)) // USB Endpoint 7 Control Register
#define USBD_EPADR7_REG (*(PVUS)(USBD_EPADR7)) // USB Endpoint 7 Address Offset Register
#define USBD_EPLEN7_REG (*(PVUS)(USBD_EPLEN7)) // USB Endpoint 7 Buffer Length Register
/*==================================================================================
// System Bus Interface Unit (0xFFC0 4800-0xFFC0 4FFF)
====================================================================================*/
#define L1SBAR_REG (*(PVUL)(L1SBAR)) // L1 SRAM Base Address Register
#define L1CSR_REG (*(PVUL)(L1CSR)) // L1 SRAM Control Initialization Register
#define DB_NDBP_REG (*(PVUL)(DB_NDBP)) // Next Descriptor Base Pointer
#define DB_ACOMP_REG (*(PVUL)(DB_ACOMP)) // DMA Bus Address Comparator
#define DB_CCOMP_REG (*(PVUL)(DB_CCOMP)) // DMA Bus Control Comparator
/*==================================================================================
// SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF)
====================================================================================*/
#define EBIU_SDGCTL_REG (*(PVUL)(EBIU_SDGCTL)) // SDRAM Global Control Register
#define EBIU_SDBCTL_REG (*(PVUL)(EBIU_SDBCTL)) // SDRAM Bank Control Register
#define EBIU_SDRRC_REG (*(PVUL)(EBIU_SDRRC)) // SDRAM Refresh Rate Control Register
#define EBIU_SDSTAT_REG (*(PVUL)(EBIU_SDSTAT)) // SDRAM Status Register
/*==================================================================================
// Event/Interrupt Registers
====================================================================================*/
#define EVT0_REG (*(PVUL)(EVT0)) // Event Vector 0 ESR Address
#define EVT1_REG (*(PVUL)(EVT1)) // Event Vector 1 ESR Address
#define EVT2_REG (*(PVUL)(EVT2)) // Event Vector 2 ESR Address
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