pcb_project1.prjpcb

单片机交通灯 源程序+原理图+PCB图

[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=
LogFolderPath=
ReleasesFolder=
ReleaseVaultGUID=
ReleaseVaultName=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchiveProject=0
TimestampOutput=0
SeparateFolders=0
TemplateLocationPath=
PinSwapBy_Netlabel=1
PinSwapBy_Pin=1
AllowPortNetNames=0
AllowSheetEntryNetNames=1
AppendSheetNumberToLocalNets=0
NetlistSinglePinNets=0
DefaultConfiguration=
UserID=0xFFFFFFFF
DefaultPcbProtel=1
DefaultPcbPcad=0
ReorderDocumentsOnCompile=1
NameNetsHierarchically=0
PowerPortNamesTakePriority=0
PushECOToAnnotationFile=1
DItemRevisionGUID=

[Document1]
DocumentPath=D:\Users\Public\Documents\Altium\AD 10\Library\jiaojiao.PcbLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0

[Document2]
DocumentPath=Sheet1.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0

[Document3]
DocumentPath=PCB1.PcbDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0

[Document4]
DocumentPath=PcbLib1.PcbLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0

[Document5]
DocumentPath=PcbLib2.PcbLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0

[Document6]
DocumentPath=PCB2.PcbDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0

[Document7]
DocumentPath=PCB3.PcbDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotationIndexControlEnabled=0
AnnotateSuffix=
AnnotateScope=All
AnnotateOrder=-1
DoLibraryUpdate=1
DoDatabaseUpdate=1
ClassGenCCAutoEnabled=1
ClassGenCCAutoRoomEnabled=1
ClassGenNCAutoScope=None
DItemRevisionGUID=
GenerateClassCluster=0

[GeneratedDocument1]
DocumentPath=Project Outputs for PCB_Project1\Sheet1.NET
DItemRevisionGUID=

[PCBConfiguration1]
ReleaseItemId=
CurrentRevision=
Name=Default Configuration
Variant=[No Variations]
GenerateBOM=0

[OutputGroup1]
Name=Netlist Outputs
Description=
TargetPrinter=Fax
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=CadnetixNetlist
OutputName1=Cadnetix Netlist
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
OutputType2=CalayNetlist
OutputName2=Calay Netlist
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=EDIF
OutputName3=EDIF for PCB
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
OutputType4=EESofNetlist
OutputName4=EESof Netlist
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
OutputType5=IntergraphNetlist
OutputName5=Intergraph Netlist
OutputDocumentPath5=
OutputVariantName5=
OutputDefault5=0
OutputType6=MentorBoardStationNetlist
OutputName6=Mentor BoardStation Netlist
OutputDocumentPath6=
OutputVariantName6=
OutputDefault6=0
OutputType7=MultiWire
OutputName7=MultiWire
OutputDocumentPath7=
OutputVariantName7=
OutputDefault7=0
OutputType8=OrCadPCB2Netlist
OutputName8=Orcad/PCB2 Netlist
OutputDocumentPath8=
OutputVariantName8=
OutputDefault8=0
OutputType9=PADSNetlist
OutputName9=PADS ASCII Netlist
OutputDocumentPath9=
OutputVariantName9=
OutputDefault9=0
OutputType10=Pcad
OutputName10=Pcad for PCB
OutputDocumentPath10=
OutputVariantName10=
OutputDefault10=0
OutputType11=PCADNetlist
OutputName11=PCAD Netlist
OutputDocumentPath11=
OutputVariantName11=
OutputDefault11=0
OutputType12=PCADnltNetlist
OutputName12=PCADnlt Netlist
OutputDocumentPath12=
OutputVariantName12=
OutputDefault12=0
OutputType13=Protel2Netlist
OutputName13=Protel2 Netlist
OutputDocumentPath13=
OutputVariantName13=
OutputDefault13=0
Configuration13_Name1=OutputConfigurationParameter1
Configuration13_Item1=??
OutputType14=ProtelNetlist
OutputName14=Protel
OutputDocumentPath14=
OutputVariantName14=
OutputDefault14=0
Configuration14_Name1=OutputConfigurationParameter1
Configuration14_Item1=NetlistVersion=0|Record=ProtelNetlistView
OutputType15=RacalNetlist
OutputName15=Racal Netlist
OutputDocumentPath15=
OutputVariantName15=
OutputDefault15=0
OutputType16=RINFNetlist
OutputName16=RINF Netlist
OutputDocumentPath16=
OutputVariantName16=
OutputDefault16=0
OutputType17=SciCardsNetlist
OutputName17=SciCards Netlist
OutputDocumentPath17=
OutputVariantName17=
OutputDefault17=0
OutputType18=SIMetrixNetlist
OutputName18=SIMetrix
OutputDocumentPath18=
OutputVariantName18=
OutputDefault18=0
OutputType19=SIMPLISNetlist
OutputName19=SIMPLIS
OutputDocumentPath19=
OutputVariantName19=
OutputDefault19=0
OutputType20=TangoNetlist
OutputName20=Tango Netlist
OutputDocumentPath20=
OutputVariantName20=
OutputDefault20=0
OutputType21=TelesisNetlist
OutputName21=Telesis Netlist
OutputDocumentPath21=
OutputVariantName21=
OutputDefault21=0
OutputType22=Verilog
OutputName22=Verilog File
OutputDocumentPath22=
OutputVariantName22=
OutputDefault22=0
OutputType23=VHDL
OutputName23=VHDL File
OutputDocumentPath23=
OutputVariantName23=
OutputDefault23=0
OutputType24=WireListNetlist
OutputName24=WireList Netlist
OutputDocumentPath24=
OutputVariantName24=
OutputDefault24=0
OutputType25=XSpiceNetlist
OutputName25=XSpice Netlist
OutputDocumentPath25=
OutputVariantName25=
OutputDefault25=0

[OutputGroup2]
Name=Simulator Outputs
Description=
TargetPrinter=Fax
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=AdvSimNetlist
OutputName1=Mixed Sim
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
OutputType2=SIMetrix_Sim
OutputName2=SIMetrix
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
OutputType3=SIMPLIS_Sim
OutputName3=SIMPLIS
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0

[OutputGroup3]
Name=Documentation Outputs
Description=
TargetPrinter=Fax
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=Assembler Source Print
OutputName1=Assembler Source Prints
OutputDocumentPath1=
OutputVariantName1=
OutputDefault1=0
PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType2=C Source Print
OutputName2=C Source Prints
OutputDocumentPath2=
OutputVariantName2=
OutputDefault2=0
PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType3=C/C++ Header Print
OutputName3=C/C++ Header Prints
OutputDocumentPath3=
OutputVariantName3=
OutputDefault3=0
PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType4=C++ Source Print
OutputName4=C++ Source Prints
OutputDocumentPath4=
OutputVariantName4=
OutputDefault4=0
PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType5=Composite
OutputName5=Composite Drawing
OutputDocumentPath5=
OutputVariantName5=
OutputDefault5=0
PageOptions5=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4|PrintScaleMode=1
OutputType6=Logic Analyser Print