deccount.tan.rpt

altera Quartus II 減法器使用 配合LED

+-------+--------------+------------+-------------+--------+------------+
; N/A   ; None         ; 16.700 ns  ; OUTCLK~reg0 ; OUTCLK ; INCLK      ;
+-------+--------------+------------+-------------+--------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; th                                                                                                                                   ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Minimum Slack ; Required th ; Actual th ; From      ; To                                                                  ; To Clock ;
+---------------+-------------+-----------+-----------+---------------------------------------------------------------------+----------+
; N/A           ; None        ; 4.500 ns  ; PRESET[3] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; INCLK    ;
; N/A           ; None        ; 4.500 ns  ; PRESET[2] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; INCLK    ;
; N/A           ; None        ; 4.300 ns  ; PRESET[1] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; INCLK    ;
; N/A           ; None        ; 4.300 ns  ; PRESET[1] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; INCLK    ;
; N/A           ; None        ; 4.300 ns  ; PRESET[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; INCLK    ;
; N/A           ; None        ; 4.300 ns  ; PRESET[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; INCLK    ;
; N/A           ; None        ; 4.200 ns  ; PRESET[2] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; INCLK    ;
; N/A           ; None        ; 3.600 ns  ; PRESET[1] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; INCLK    ;
; N/A           ; None        ; 3.600 ns  ; PRESET[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; INCLK    ;
; N/A           ; None        ; 3.400 ns  ; PRESET[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; INCLK    ;
+---------------+-------------+-----------+-----------+---------------------------------------------------------------------+----------+


+---------------------------------------------------------------------------------------+
; Minimum tco                                                                           ;
+----------------------------------------------------------------------------------------
; Minimum Slack ; Required Min tco ; Actual Min tco ; From        ; To     ; From Clock ;
+---------------+------------------+----------------+-------------+--------+------------+
; N/A           ; None             ; 16.700 ns      ; OUTCLK~reg0 ; OUTCLK ; INCLK      ;
+---------------+------------------+----------------+-------------+--------+------------+


+---------------------------+
; Timing Analyzer Messages  ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Thu Dec 16 19:05:09 2004
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off deccount -c deccount
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Found combinational loop of 3 nodes
    Info: Node i4
    Info: Node OUTCLK~reg0
    Info: Node reg_G_divide
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node INCLK is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock i4 as buffer
Info: Clock INCLK Internal fmax is restricted to 200.0 MHz between source register reg_G_divide and destination register reg_G_divide
    Info: fmax restricted to Clock High delay (2.5 ns) plus Clock Low delay (2.5 ns) : restricted to 5.0 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.100 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_F26; Fanout = 2; REG Node = 'reg_G_divide'
            Info: 2: + IC(0.300 ns) + CELL(0.800 ns) = 1.100 ns; Loc. = LC2_F26; Fanout = 2; REG Node = 'reg_G_divide'
            Info: Total cell delay = 0.800 ns ( 72.73 % )
            Info: Total interconnect delay = 0.300 ns ( 27.27 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock INCLK to destination register is 10.300 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 2; CLK Node = 'INCLK'
                Info: 2: + IC(0.000 ns) + CELL(1.800 ns) = 3.800 ns; Loc. = LC1_F26; Fanout = 6; COMB LOOP Node = 'i4'
                    Info: Loc. = LC2_F26; Node reg_G_divide
                Info: 3: + IC(4.700 ns) + CELL(0.500 ns) = 9.000 ns; Loc. = LC1_F20; Fanout = 2; REG Node = 'OUTCLK~reg0'
                Info: 4: + IC(1.300 ns) + CELL(0.000 ns) = 10.300 ns; Loc. = LC2_F26; Fanout = 2; REG Node = 'reg_G_divide'
                Info: Total cell delay = 4.300 ns ( 41.75 % )
                Info: Total interconnect delay = 6.000 ns ( 58.25 % )
            Info: - Longest clock path from clock INCLK to source register is 10.300 ns
                Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 2; CLK Node = 'INCLK'
                Info: 2: + IC(0.000 ns) + CELL(1.800 ns) = 3.800 ns; Loc. = LC1_F26; Fanout = 6; COMB LOOP Node = 'i4'
                    Info: Loc. = LC2_F26; Node reg_G_divide
                Info: 3: + IC(4.700 ns) + CELL(0.500 ns) = 9.000 ns; Loc. = LC1_F20; Fanout = 2; REG Node = 'OUTCLK~reg0'
                Info: 4: + IC(1.300 ns) + CELL(0.000 ns) = 10.300 ns; Loc. = LC2_F26; Fanout = 2; REG Node = 'reg_G_divide'
                Info: Total cell delay = 4.300 ns ( 41.75 % )
                Info: Total interconnect delay = 6.000 ns ( 58.25 % )
        Info: + Micro clock to output delay of source is 0.500 ns
        Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] (data pin = PRESET[0], clock pin = INCLK) is -1.500 ns
    Info: + Longest pin to register delay is 6.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_124; Fanout = 4; PIN Node = 'PRESET[0]'
        Info: 2: + IC(0.500 ns) + CELL(1.600 ns) = 4.100 ns; Loc. = LC2_F24; Fanout = 1; COMB Node = 'i~10'
        Info: 3: + IC(1.300 ns) + CELL(1.000 ns) = 6.400 ns; Loc. = LC5_F20; Fanout = 5; REG Node = 'lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]'
        Info: Total cell delay = 4.600 ns ( 71.88 % )
        Info: Total interconnect delay = 1.800 ns ( 28.13 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock INCLK to destination register is 8.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 2; CLK Node = 'INCLK'
        Info: 2: + IC(0.000 ns) + CELL(1.800 ns) = 3.800 ns; Loc. = LC1_F26; Fanout = 6; COMB LOOP Node = 'i4'
            Info: Loc. = LC2_F26; Node reg_G_divide
        Info: 3: + IC(4.700 ns) + CELL(0.000 ns) = 8.500 ns; Loc. = LC5_F20; Fanout = 5; REG Node = 'lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1]'
        Info: Total cell delay = 3.800 ns ( 44.71 % )
        Info: Total interconnect delay = 4.700 ns ( 55.29 % )
Info: tco from clock INCLK to destination pin OUTCLK through register OUTCLK~reg0 is 16.700 ns
    Info: + Longest clock path from clock INCLK to source register is 8.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 2; CLK Node = 'INCLK'
        Info: 2: + IC(0.000 ns) + CELL(1.800 ns) = 3.800 ns; Loc. = LC1_F26; Fanout = 6; COMB LOOP Node = 'i4'
            Info: Loc. = LC2_F26; Node reg_G_divide
        Info: 3: + IC(4.700 ns) + CELL(0.000 ns) = 8.500 ns; Loc. = LC1_F20; Fanout = 2; REG Node = 'OUTCLK~reg0'
        Info: Total cell delay = 3.800 ns ( 44.71 % )
        Info: Total interconnect delay = 4.700 ns ( 55.29 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 7.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F20; Fanout = 2; REG Node = 'OUTCLK~reg0'
        Info: 2: + IC(1.400 ns) + CELL(6.300 ns) = 7.700 ns; Loc. = Pin_30; Fanout = 0; PIN Node = 'OUTCLK'
        Info: Total cell delay = 6.300 ns ( 81.82 % )
        Info: Total interconnect delay = 1.400 ns ( 18.18 % )
Info: th for register lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] (data pin = PRESET[3], clock pin = INCLK) is 4.500 ns
    Info: + Longest clock path from clock INCLK to destination register is 8.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 2; CLK Node = 'INCLK'
        Info: 2: + IC(0.000 ns) + CELL(1.800 ns) = 3.800 ns; Loc. = LC1_F26; Fanout = 6; COMB LOOP Node = 'i4'
            Info: Loc. = LC2_F26; Node reg_G_divide
        Info: 3: + IC(4.700 ns) + CELL(0.000 ns) = 8.500 ns; Loc. = LC7_F20; Fanout = 4; REG Node = 'lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 3.800 ns ( 44.71 % )
        Info: Total interconnect delay = 4.700 ns ( 55.29 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 5.300 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_55; Fanout = 1; PIN Node = 'PRESET[3]'
        Info: 2: + IC(0.600 ns) + CELL(1.400 ns) = 4.000 ns; Loc. = LC3_F20; Fanout = 1; COMB Node = 'i~20'
        Info: 3: + IC(0.300 ns) + CELL(1.000 ns) = 5.300 ns; Loc. = LC7_F20; Fanout = 4; REG Node = 'lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 4.400 ns ( 83.02 % )
        Info: Total interconnect delay = 0.900 ns ( 16.98 % )
Info: Minimum tco from clock INCLK to destination pin OUTCLK through register OUTCLK~reg0 is 16.700 ns
    Info: + Shortest clock path from clock INCLK to source register is 8.500 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = Pin_125; Fanout = 2; CLK Node = 'INCLK'
        Info: 2: + IC(0.000 ns) + CELL(1.800 ns) = 3.800 ns; Loc. = LC1_F26; Fanout = 6; COMB LOOP Node = 'i4'
            Info: Loc. = LC2_F26; Node reg_G_divide
        Info: 3: + IC(4.700 ns) + CELL(0.000 ns) = 8.500 ns; Loc. = LC1_F20; Fanout = 2; REG Node = 'OUTCLK~reg0'
        Info: Total cell delay = 3.800 ns ( 44.71 % )
        Info: Total interconnect delay = 4.700 ns ( 55.29 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Shortest register to pin delay is 7.700 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F20; Fanout = 2; REG Node = 'OUTCLK~reg0'
        Info: 2: + IC(1.400 ns) + CELL(6.300 ns) = 7.700 ns; Loc. = Pin_30; Fanout = 0; PIN Node = 'OUTCLK'
        Info: Total cell delay = 6.300 ns ( 81.82 % )
        Info: Total interconnect delay = 1.400 ns ( 18.18 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu Dec 16 19:05:11 2004
    Info: Elapsed time: 00:00:01