📄 deccount.tan.rpt
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Timing Analyzer report for deccount
Thu Dec 16 19:05:11 2004
Version 4.0 Build 190 1/28/2004 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Timing Analyzer Settings
3. Timing Analyzer Summary
4. Clock Settings Summary
5. Clock Setup: 'INCLK'
6. tsu
7. tco
8. th
9. Minimum tco
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
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other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
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limited to modification, reverse engineering, de-compiling, or use with
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intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
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licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+----------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-----------------------------------------------------------------------------------------
; Option ; Setting ; From ; To ;
+-------------------------------------------------------+--------------------+------+----+
; Device name ; EP1K30TC144-3 ; ; ;
; Report IO Paths Separately ; Off ; ; ;
; Ignore user-defined clock settings ; Off ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ;
; Cut off feedback from I/O pins ; On ; ; ;
; Cut off clear and preset signal paths ; On ; ; ;
; Cut off read during write signal paths ; On ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ;
; Run Minimum Analysis ; On ; ; ;
; Use Minimum Timing Models ; Off ; ; ;
; Number of paths to report ; 200 ; ; ;
; Number of destination nodes to report ; 10 ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ;
+-------------------------------------------------------+--------------------+------+----+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Type ; Slack ; Required Time ; Actual Time ; From ; To ;
+------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------+---------------------------------------------------------------------+
; Worst-case tsu ; N/A ; None ; -1.500 ns ; PRESET[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ;
; Worst-case tco ; N/A ; None ; 16.700 ns ; OUTCLK~reg0 ; OUTCLK ;
; Worst-case th ; N/A ; None ; 4.500 ns ; PRESET[2] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ;
; Worst-case minimum tco ; N/A ; None ; 16.700 ns ; OUTCLK~reg0 ; OUTCLK ;
; Clock Setup: 'INCLK' ; N/A ; None ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ;
+------------------------+-------+---------------+------------------------------------------------+---------------------------------------------------------------------+---------------------------------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+---------------------------------------------------------------------------------------------------------------------------------------
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; INCLK ; ; User Pin ; NONE ; NONE ; N/A ; N/A ; N/A ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'INCLK' ;
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; reg_G_divide ; reg_G_divide ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; OUTCLK~reg0 ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; OUTCLK~reg0 ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; OUTCLK~reg0 ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; OUTCLK~reg0 ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; INCLK ; INCLK ; None ; None ; None ;
; N/A ; Restricted to 200.00 MHz ( period = 5.000 ns ) ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; INCLK ; INCLK ; None ; None ; None ;
+-------+------------------------------------------------+---------------------------------------------------------------------+---------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------------------------------------------------------------------------+
; tsu ;
+---------------------------------------------------------------------------------------------------------------------------------
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+-----------+---------------------------------------------------------------------+----------+
; N/A ; None ; -1.500 ns ; PRESET[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; INCLK ;
; N/A ; None ; -1.700 ns ; PRESET[1] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; INCLK ;
; N/A ; None ; -1.700 ns ; PRESET[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; INCLK ;
; N/A ; None ; -2.300 ns ; PRESET[2] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; INCLK ;
; N/A ; None ; -2.400 ns ; PRESET[1] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; INCLK ;
; N/A ; None ; -2.400 ns ; PRESET[1] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; INCLK ;
; N/A ; None ; -2.400 ns ; PRESET[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; INCLK ;
; N/A ; None ; -2.400 ns ; PRESET[0] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; INCLK ;
; N/A ; None ; -2.600 ns ; PRESET[3] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; INCLK ;
; N/A ; None ; -2.600 ns ; PRESET[2] ; lpm_counter:reg_G_Counter_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; INCLK ;
+-------+--------------+------------+-----------+---------------------------------------------------------------------+----------+
+-----------------------------------------------------------------------+
; tco ;
+------------------------------------------------------------------------
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
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