📄 early_init.s
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#define MC3_RAS6P 0 /* 0-15 */#define MC3_CAS5 0 /* 0-7 */#define MC3_CP4 0 /* 0-7 */#define MC3_CAS3 0 /* 0-7 */#define MC3_RCD2 0 /* 0-7 */#define MC3_RP1 0 /* 0-7 */ LOADPTR (r3, MEM_CONT3_ADR) /* Set MCCR3 (F8) */ stwbrx r3,0,r5 LOADPTR(r4, \ MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \ MC3_RDLAT << 20 | MC3_CPX << 19 | \ MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \ MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1) cmpl 0, 0, r7, r9 /* Check for Kahlua2 */ bne notK2b /* clear Kahlua2 reserved bits */ LOADPTR (r3, 0xff000000) and r4, r4, r3notK2b: stwbrx r4,0,r6 /*------- MCCR4 */#define MC4_PRETOACT 3 /* 0-15 */#define MC4_ACTOPRE 5 /* 0-15 */#define MC4_WMODE 0 /* 0-1 */#define MC4_INLINE MC_ECC /* 0-1 */#define MC4_REGISTERED (1-MC_ECC) /* 0-1 */#define MC4_BSTOPRE_UU (MC_BSTOPRE >> 8 & 3)#define MC4_REGDIMM 0 /* 0-1 */#define MC4_SDMODE_CAS 2 /* 0-7 */#define MC4_DBUS_RCS1 1 /* 0-1, 8-bit */#define MC4_SDMODE_WRAP 0 /* 0-1 */#define MC4_SDMODE_BURST 2 /* 0-7 */#define MC4_ACTORW 3 /* 0-15 */#define MC4_BSTOPRE_L (MC_BSTOPRE & 0xf) LOADPTR (r3, MEM_CONT4_ADR) /* Set MCCR4 (FC) */ stwbrx r3,0,r5 LOADPTR(r4, \ MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \ MC4_WMODE << 23 | MC4_INLINE << 22 | \ MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \ MC4_DBUS_RCS1 << 17 | \ MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \ MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \ MC4_ACTORW << 4 | MC4_BSTOPRE_L) cmpl 0, 0, r7, r9 /* Check for Kahlua 2 */ bne notK2c /* Turn on Kahlua2 extended ROM space */ LOADPTR (r3, 0x00200000) or r4, r4, r3notK2c: stwbrx r4,0,r6#ifdef INCLUDE_ECC /*------- MEM_ERREN1 */ LOADPTR (r3, MEM_ERREN1_ADR) /* Set MEM_ERREN1 (c0) */ stwbrx r3,0,r5 lwbrx r4,0,r6 ori r4,r4,4 /* Set MEM_PERR_EN */ stwbrx r4,0,r6#endif /* INCLUDE_ECC */ /*------- MSAR/MEAR */ LOADPTR (r3, MEM_START1_ADR) /* Set MSAR1 (80) */ stwbrx r3,0,r5 LOADPTR (r4, 0xc0804000) stwbrx r4,0,r6 LOADPTR (r3, MEM_START2_ADR) /* Set MSAR2 (84) */ stwbrx r3,0,r5 LOADPTR (r4, 0xc0804000) stwbrx r4,0,r6 LOADPTR (r3, XMEM_START1_ADR) /* Set MESAR1 (88) */ stwbrx r3,0,r5 LOADPTR (r4, 0x00000000) stwbrx r4,0,r6 LOADPTR (r3, XMEM_START2_ADR) /* Set MESAR2 (8c) */ stwbrx r3,0,r5 LOADPTR (r4, 0x01010101) stwbrx r4,0,r6 LOADPTR (r3, MEM_END1_ADR) /* Set MEAR1 (90) */ stwbrx r3,0,r5 LOADPTR (r4, 0xffbf7f3f) stwbrx r4,0,r6 LOADPTR (r3, MEM_END2_ADR) /* Set MEAR2 (94) */ stwbrx r3,0,r5 LOADPTR (r4, 0xffbf7f3f) stwbrx r4,0,r6 LOADPTR (r3, XMEM_END1_ADR) /* MEEAR1 (98) */ stwbrx r3,0,r5 LOADPTR (r4, 0x00000000) stwbrx r4,0,r6 LOADPTR (r3, XMEM_END2_ADR) /* MEEAR2 (9c) */ stwbrx r3,0,r5 LOADPTR (r4, 0x01010101) stwbrx r4,0,r6 /*-------ODCR */ LOADPTR (r3, ODCR_ADR_X) /* Set ODCR */ stwbrx r3,0,r5 li r4, 0x7f stb r4, ODCR_SHIFT(r6) /* ODCR is at +3 offset */ /*-------MBEN */ LOADPTR (r3, MEM_EN_ADR) /* Set MBEN (a0) */ stwbrx r3,0,r5 li r4, 0x01 /* Enable bank 0 */ stb r4, 0(r6) /* MBEN is at +0 offset */#if 0 /* Jimmy: I think page made is broken */ /*-------PGMAX */ LOADPTR (r3, MPM_ADR_X) stwbrx r3,0,r5 li r4, 0x32 stb r4, MPM_SHIFT(r6) /* PAGE_MODE is at +3 offset */#endif /* Wait before initializing other registers */ lis r4,0x0001 mtctr r4KahluaX4wait200us: bdnz KahluaX4wait200us /* Set MEMGO bit */ LOADPTR (r3, MEM_CONT1_ADR) /* MCCR1 (F0) |= PGMAX */ stwbrx r3,0,r5 lwbrx r4,0,r6 /* old MCCR1 */ oris r4,r4,0x0008 /* MEMGO=1 */ stwbrx r4, 0, r6 /* Wait again */ addis r4,r0,0x0002 ori r4,r4,0xffff mtctr r4KahluaX4wait8ref: bdnz KahluaX4wait8ref sync eieio mtlr r11 blr#else /* USE_V2_INIT *//* U-Boot works, but memory will not run reliably for all address ranges. * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not * initialized correctly. Could work if debugged. *//* PCI Support routines */ .globl __pci_config_read_32__pci_config_read_32: lis r4, 0xfec0 stwbrx r3, r0, r4 sync lis r4, 0xfee0 lwbrx r3, 0, r4 blr .globl __pci_config_read_16__pci_config_read_16: lis r4, 0xfec0 andi. r5, r3, 2 stwbrx r3, r0, r4 sync oris r4, r5, 0xfee0 lhbrx r3, r0, r4 blr .globl __pci_config_read_8__pci_config_read_8: lis r4, 0xfec0 andi. r5, r3, 3 stwbrx r3, r0, r4 sync oris r4, r5, 0xfee0 lbz r3, 0(4) blr .globl __pci_config_write_32__pci_config_write_32: lis r5, 0xfec0 stwbrx r3, r0, r5 sync lis r5, 0xfee0 stwbrx r4, r0, r5 sync blr .globl __pci_config_write_16__pci_config_write_16: lis r5, 0xfec0 andi. r6, r3, 2 stwbrx r3, r0, 5 sync oris r5, r6, 0xfee0 sthbrx r4, r0, r5 sync blr .globl __pci_config_write_8__pci_config_write_8: lis r5, 0xfec0 andi. r6, r3, 3 stwbrx r3, r0, r5 sync oris r5, r6, 0xfee0 stb r4, 0(r5) sync blr .globl in_8in_8: oris r3, r3, 0xfe00 lbz r3,0(r3) blr .globl in_16in_16: oris r3, r3, 0xfe00 lhbrx r3, 0, r3 blr .globl in_16_nein_16_ne: oris r3, r3, 0xfe00 lhzx r3, 0, r3 blr .globl in_32in_32: oris r3, r3, 0xfe00 lwbrx r3, 0, r3 blr .globl out_8out_8: oris r3, r3, 0xfe00 stb r4, 0(r3) eieio blr .globl out_16out_16: oris r3, r3, 0xfe00 sthbrx r4, 0, r3 eieio blr .globl out_16_neout_16_ne: oris r3, r3, 0xfe00 sth r4, 0(r3) eieio blr .globl out_32out_32: oris r3, r3, 0xfe00 stwbrx r4, 0, r3 eieio blr .globl read_8read_8: lbz r3,0(r3) blr .globl read_16read_16: lhbrx r3, 0, r3 blr .globl read_32read_32: lwbrx r3, 0, r3 blr .globl read_32_neread_32_ne: lwz r3, 0(r3) blr .globl write_8write_8: stb r4, 0(r3) eieio blr .globl write_16write_16: sthbrx r4, 0, r3 eieio blr .globl write_32write_32: stwbrx r4, 0, r3 eieio blr .globl write_32_newrite_32_ne: stw r4, 0(r3) eieio blr.globl early_init_fearly_init_f: mflr r11 lis r10, 0x8000 /* PCI Latency Timer */ li r4, 0x0d ori r3, r10, PLTR@l bl __pci_config_write_8 /* Cache Line Size */ li r4, 0x08 ori r3, r10, PCLSR@l bl __pci_config_write_8 /* PCI Cmd */ li r4, 6 ori r3, r10, PCICR@l bl __pci_config_write_16#if 1 /* PCI Stat */ ori r3, r10, PCISR@l bl __pci_config_read_16 ori r4, r4, 0xffff ori r3, r10, PCISR@l bl __pci_config_write_16#endif /* PICR1 */ lis r4, 0xff14 ori r4, r4, 0x1b98 ori r3, r10, PICR1@l bl __pci_config_write_32 /* PICR2 */ lis r4, 0x0404 ori r4, r4, 0x0004 ori r3, r10, PICR2@l bl __pci_config_write_32 /* MIOCR1 */ li r4, 0x04 ori r3, r10, MIOCR1@l bl __pci_config_write_8 /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */ /* SDRAM_CLK_DEL (0x77)*/ li r4, 0x10 ori r3, r10, MIOCR2@l bl __pci_config_write_8 /* EUMBBAR */ lis r4, 0xfc00 ori r3, r10, EUMBBAR@l bl __pci_config_write_32 /* AMBOR */ /* Even if Address Map B is not being used (though it should), * the memory DLL needs to be cleared/set/cleared before using memory. */ ori r3, r10, AMBOR@l bl __pci_config_read_8 /* get Current bits */ andi. r4, r4, 0xffdf ori r3, r10, AMBOR@l bl __pci_config_write_16 /* Clear DLL_RESET */ ori r4, r4, 0x0020 ori r3, r10, AMBOR@l bl __pci_config_write_16 /* Set DLL_RESET */ andi. r4, r4, 0xffdf ori r3, r10, AMBOR@l bl __pci_config_write_16 /* Clear DLL_RESET */ /* ERCR1 */ lis r4, 0x8040 /* Enable RCS2, use supplied timings */ ori r4, r4, 0x8000 ori r3, r10, ERCR1@l bl __pci_config_write_32 /* ERCR2 */ lis r4, 0x0000 /* Disable RCS3 parms */ ori r4, r4, 0x0000 ori r3, r10, ERCR2@l bl __pci_config_write_32 /* ERCR3 */ lis r4, 0x0000 /* RCS3 at 0x70000000, 64K bytes */ ori r4, r4, 0x0004 ori r3, r10, ERCR2@l bl __pci_config_write_32 /* Preserve memgo bit */ /* MCCR1 *//* lis r4, 0x75a8 / Safe Local ROM = 11+3 clocks */ lis r4, 0x75a0 /* Safe Local ROM = 11+3 clocks *//* lis r4, 0x73a0 / Fast Local ROM = 7+3 clocks *//* oris r4, r4, 0x0010 / Burst ROM/Flash enable *//* oris r4, r4, 0x0004 / Self-refresh enable *//* ori r4,r4,0xFFFF / 16Mbit 2bank SDRAM *//* ori r4,r4,0xAAAA / 256Mbit 4bank SDRAM (8245 only) *//* ori r4,r4,0x5555 / 64Mbit 2bank SDRAM */ ori r4,r4,0x0000 /* 64Mbit 4bank SDRAM */ ori r3, r10, MCCR1@l bl __pci_config_write_32 /* MCCR2 */ lis r4,0x0000/* oris r4,r4,0x4000 / TS_WAIT_TIMER = 3 clocks */ oris r4,r4,0x1000 /* ASRISE = 8 clocks */ oris r4,r4,0x0080 /* ASFALL = 8 clocks *//* oris r4,r4,0x0010 / SDRAM Parity (else ECC) *//* oris r4,r4,0x0008 / Write parity check *//* oris r4,r4,0x0004 / SDRAM inline reads *//* Select a refresh rate; it needs to match the bus speed; if too *//* slow, data may be lost; if too fast, performance is lost. We *//* use the fastest value so we run at all speeds. *//* Refresh = (15600ns/busclk) - (213 (see UM)). *//* ori r4,r4,0x1d2c / 133 MHz mem bus = 1867 *//* ori r4,r4,0x150c / 100 MHz mem bus = 1347 *//* ori r4,r4,0x10fc / 83 MHz mem bus = 1087 *//* ori r4,r4,0x0cc4 / 66 MHz mem bus = 817 */ ori r4,r4,0x04cc /* 33 MHz mem bus (SAFE) = 307 *//* ori r4,r4,0x0002 / Reserve a page *//* ori r4,r4,0x0001 / RWM parity */ ori r3, r10, MCCR2@l bl __pci_config_write_32 /* MCCR3 */ lis r4,0x0000 /* BSTOPRE_M = 7 (see A/N) */ oris r4,r4,0x0500 /* REFREC = 8 clocks */ ori r3, r10, MCCR3@l bl __pci_config_write_32 /* MCCR4 */ /* Turn on registered buffer mode */ lis r4, 0x2000 /* PRETOACT = 3 clocks */ oris r4,r4,0x0400 /* ACTOPRE = 5 clocks *//* oris r4,r4,0x0080 / Enable 8-beat burst (32-bit bus) *//* oris r4,r4,0x0040 / Enable Inline ECC/Parity */ oris r4,r4,0x0020 /* EXTROM enabled */ oris r4,r4,0x0010 /* Registered buffers *//* oris r4,r4,0x0000 / BSTOPRE_U = 0 (see A/N) */ oris r4,r4,0x0002 /* DBUS_SIZ[2] (8 bit on RCS1) *//* ori r4,r4,0x8000 / Registered DIMMs */ ori r4,r4,0x2000 /*CAS Latency (CL=3) (see RDLAT) *//* ori r4,r4,0x2000 / CAS Latency (CL=2) (see RDLAT) *//* ori r4,r4,0x0300 / Sequential wrap/8-beat burst */ ori r4,r4,0x0200 /* Sequential wrap/4-beat burst */ ori r4,r4,0x0030 /* ACTORW = 3 clocks */ ori r4,r4,0x0009 /* BSTOPRE_L = 9 (see A/N) */ ori r3, r10, MCCR4@l bl __pci_config_write_32 /* MSAR1 */ lis r4, 0xc0804000@h ori r4, r4, 0xc0804000@l ori r3, r10, MSAR1@l bl __pci_config_write_32 /* MSAR2 */ lis r4, 0xc0804000@h ori r4, r4, 0xc0804000@l ori r3, r10, MSAR2@l bl __pci_config_write_32 /* MESAR1 */ lis r4, 0x00000000@h ori r4, r4, 0x00000000@l ori r3, r10, EMSAR1@l bl __pci_config_write_32 /* MESAR2 */ lis r4, 0x01010101@h ori r4, r4, 0x01010101@l ori r3, r10, EMSAR2@l bl __pci_config_write_32 /* MEAR1 */ lis r4, 0xffbf7f3f@h ori r4, r4, 0xffbf7f3f@l ori r3, r10, MEAR1@l bl __pci_config_write_32 /* MEAR2 */ lis r4, 0xffbf7f3f@h ori r4, r4, 0xffbf7f3f@l ori r3, r10, MEAR2@l bl __pci_config_write_32 /* MEEAR1 */ lis r4, 0x00000000@h ori r4, r4, 0x00000000@l ori r3, r10, EMEAR1@l bl __pci_config_write_32 /* MEEAR2 */ lis r4, 0x01010101@h ori r4, r4, 0x01010101@l ori r3, r10, EMEAR2@l bl __pci_config_write_32 /* ODCR */ li r4, 0x7f ori r3, r10, ODCR@l bl __pci_config_write_8 /* MBER */ li r4, 0x01 ori r3, r10, MBER@l bl __pci_config_write_8 /* Page CTR aka PGMAX */ li r4, 0x32 ori r3, r10, 0x70 bl __pci_config_write_8#if 0 /* CLK Drive */ ori r4, r10, 0xfc01 /* Top bit will be ignored */ ori r3, r10, 0x74 bl __pci_config_write_16#endif /* delay */ lis r7, 1 mtctr r7label1: bdnz label1 /* Set memgo bit */ /* MCCR1 */ ori r3, r10, MCCR1@l bl __pci_config_read_32 lis r7, 0x0008 or r4, r3, r7 ori r3, r10, MCCR1@l bl __pci_config_write_32 /* delay again */ lis r7, 1 mtctr r7label2: bdnz label2#if 0/* DEBUG: Infinite loop, write then read */loop: lis r7, 0xffff mtctr r7 li r3, 0x5004 lis r4, 0xa0a0 ori r4, r4, 0x5050 bl write_32_ne li r3, 0x5004 bl read_32_ne bdnz loop#endif mtlr r11 blr#endif⌨️ 快捷键说明
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