rs_enc_m2.vhd

来自「RS编码的某个校验符 RS编码的某个校验符」· VHDL 代码 · 共 53 行

----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:25:28 10/22/2007 
-- Design Name: 
-- Module Name:    rs_enc_m2 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity rs_enc_m2 is
    Port ( x : in  STD_LOGIC_VECTOR (7 downto 0);
           y : out  STD_LOGIC_VECTOR (7 downto 0));
end rs_enc_m2;

architecture Behavioral of rs_enc_m2 is
--signal z : STD_LOGIC_VECTOR (7 downto 0);
begin
  process(x)
    begin
	 	y(0) <= x(0) XOR x(1) XOR x(2) XOR x(3) XOR x(4) XOR x(5);
		y(1) <= x(0) XOR x(6);
		y(2) <= x(0) XOR x(2) XOR x(3) XOR x(4) XOR x(5) XOR x(7);
		y(3) <= x(1) XOR x(3) XOR x(4) XOR x(5) XOR x(6);
		y(4) <= x(2) XOR x(4) XOR x(5) XOR x(6) XOR x(7);
		y(5) <= x(3) XOR x(5) XOR x(6) XOR x(7);
		y(6) <= x(4) XOR x(6) XOR x(7);
		y(7) <= x(0) XOR x(1) XOR x(2) XOR x(3) XOR x(4) XOR x(7);
		--y<=z;
	end process;

end Behavioral;