📄 6812dp256.h
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/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 1*****/
__DECL__6812DP256_H__ volatile unsigned int TC1 _IO_AT(0x52);
/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 2*****/
__DECL__6812DP256_H__ volatile unsigned int TC2 _IO_AT(0x54);
/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 3*****/
__DECL__6812DP256_H__ volatile unsigned int TC3 _IO_AT(0x56);
/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 4*****/
__DECL__6812DP256_H__ volatile unsigned int TC4 _IO_AT(0x58);
/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 5*****/
__DECL__6812DP256_H__ volatile unsigned int TC5 _IO_AT(0x5a);
/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 6*****/
__DECL__6812DP256_H__ volatile unsigned int TC6 _IO_AT(0x5c);
/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 7*****/
__DECL__6812DP256_H__ volatile unsigned int TC7 _IO_AT(0x5e);
/*******************************************************************************************/
/* PULSE ACCUMULATOR CONTROL REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _PAI:1;
unsigned char _PAOVI:1;
unsigned char _CLK0:1;
unsigned char _CLK1:1;
unsigned char _PEDGE:1;
unsigned char _PAMOD:1;
unsigned char _PAEN:1;
unsigned char BIT7:1;
} PACTL_BITS;
unsigned char PACTL_BYTE;
} PACTL1 _IO_AT(0x60);
/*DEFINE REGISTER*/
#define PACTL PACTL1.PACTL_BYTE
/*DEFINE REGISTER BITS*/
#define PAI PACTL1.PACTL_BITS._PAI
#define PAOVI PACTL1.PACTL_BITS._PAOVI
#define CLK0 PACTL1.PACTL_BITS._CLK0
#define CLK1 PACTL1.PACTL_BITS._CLK1
#define PEDGE PACTL1.PACTL_BITS._PEDGE
#define PAMOD PACTL1.PACTL_BITS._PAMOD
#define PAEN PACTL1.PACTL_BITS._PAEN
/*******************************************************************************************/
/* PULSE ACCUMULATOR FLAG REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _PAIF:1;
unsigned char _PAOVF:1;
unsigned char BIT2:1;
unsigned char BIT3:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char BIT6:1;
unsigned char BIT7:1;
} PAFLG_BITS;
unsigned char PAFLG_BYTE;
} PAFLG1 _IO_AT(0x61);
/*DEFINE REGISTER*/
#define PAFLG PAFLG1.PAFLG_BYTE
/*DEFINE REGISTER BITS*/
#define PAIF PAFLG1.PAFLG_BITS._PAIF
#define PAOVF PAFLG1.PAFLG_BITS._PAOVF
/*******************************************************************************************/
/* 16-BITS PULSE ACCUMULATOR COUNT REGISTERS */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile unsigned char PACN3 _IO_AT(0x62);
__DECL__6812DP256_H__ volatile unsigned char PACN2 _IO_AT(0x63);
__DECL__6812DP256_H__ volatile unsigned char PACN1 _IO_AT(0x64);
__DECL__6812DP256_H__ volatile unsigned char PACN0 _IO_AT(0x65);
/*******************************************************************************************/
/* 16-BIT MODULUS DOWN-COUNTER CONTROL REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _MCPR0:1;
unsigned char _MCPR1:1;
unsigned char _MCEN:1;
unsigned char _FLMC:1;
unsigned char _ICLAT:1;
unsigned char _RDMCL:1;
unsigned char _MODMC:1;
unsigned char _MCZI:1;
} MCCTL_BITS;
unsigned char MCCTL_BYTE;
} MCCTL1 _IO_AT(0x66);
/*DEFINE REGISTER*/
#define MCCTL MCCTL1.MCCTL_BYTE
/*DEFINE REGISTER BITS*/
#define MCPR0 MCCTL1.MCCTL_BITS._MCPR0
#define MCPR1 MCCTL1.MCCTL_BITS._MCPR1
#define MCEN MCCTL1.MCCTL_BITS._MCEN
#define FLMC MCCTL1.MCCTL_BITS._FLMC
#define ICLAT MCCTL1.MCCTL_BITS._ICLAT
#define RDMCL MCCTL1.MCCTL_BITS._RDMCL
#define MODMC MCCTL1.MCCTL_BITS._MODMC
#define MCZI MCCTL1.MCCTL_BITS._MCZI
/*******************************************************************************************/
/* 16-BIT MODULUS DOWN-COUNTER FLAG REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _POLF0:1;
unsigned char _POLF1:1;
unsigned char _POLF2:1;
unsigned char _POLF3:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char BIT6:1;
unsigned char _MCZF:1;
} MCFLG_BITS;
unsigned char MCFLG_BYTE;
} MCFLG1 _IO_AT(0x67);
/*DEFINE REGISTER*/
#define MCFLG MCFLG1.MCFLG_BYTE
/*DEFINE REGISTER BITS*/
#define POLF0 MCFLG1.MCFLG_BITS._POLF0
#define POLF1 MCFLG1.MCFLG_BITS._POLF1
#define POLF2 MCFLG1.MCFLG_BITS._POLF2
#define POLF3 MCFLG1.MCFLG_BITS._POLF3
#define MCZF MCFLG1.MCFLG_BITS._MCZF
/*******************************************************************************************/
/* INPUT CONTROL PULSE ACCUMULATORS REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _PA0EN:1;
unsigned char _PA1EN:1;
unsigned char _PA2EN:1;
unsigned char _PA3EN:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char BIT6:1;
unsigned char BIT7:1;
} ICPAR_BITS;
unsigned char ICPAR_BYTE;
} ICPAR1 _IO_AT(0x68);
/*DEFINE REGISTER*/
#define ICPAR ICPAR1.ICPAR_BYTE
/*DEFINE REGISTER BITS*/
#define PA0EN ICPAR1.ICPAR_BITS._PA0EN
#define PA1EN ICPAR1.ICPAR_BITS._PA1EN
#define PA2EN ICPAR1.ICPAR_BITS._PA2EN
#define PA3EN ICPAR1.ICPAR_BITS._PA3EN
/*******************************************************************************************/
/* DELAY COUNTER CONTROL REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _DLY0:1;
unsigned char _DLY1:1;
unsigned char BIT2EN:1;
unsigned char BIT3EN:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char BIT6:1;
unsigned char BIT7:1;
} DLYCT_BITS;
unsigned char DLYCT_BYTE;
} DLYCT1 _IO_AT(0x69);
/*DEFINE REGISTER*/
#define DLYCT DLYCT1.DLYCT_BYTE
/*DEFINE REGISTER BITS*/
#define DLY0 DLYCT1.DLYCT_BITS._DLY0
#define DLY1 DLYCT1.DLYCT_BITS._DLY1
/*******************************************************************************************/
/* INPUT CONTROL OVERWRITE REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile unsigned char ICOVW _IO_AT(0x6A);
/*******************************************************************************************/
/* INPUT CONTROL SYSTEM CONTROL REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _LATQ:1;
unsigned char _BUFEN:1;
unsigned char _PACMX:1;
unsigned char _TFMOD:1;
unsigned char _SH04:1;
unsigned char _SH15:1;
unsigned char _SH26:1;
unsigned char _SH37:1;
} ICSYS_BITS;
unsigned char ICSYS_BYTE;
} ICSYS1 _IO_AT(0x6B);
/*DEFINE REGISTER*/
#define ICSYS ICSYS1.ICSYS_BYTE
/*DEFINE REGISTER BITS*/
#define LATQ ICSYS1.ICSYS_BITS._LATQ
#define BUFEN ICSYS1.ICSYS_BITS._BUFEN
#define PACMX ICSYS1.ICSYS_BITS._PACMX
#define TFMOD ICSYS1.ICSYS_BITS._TFMOD
#define SH04 ICSYS1.ICSYS_BITS._SH04
#define SH15 ICSYS1.ICSYS_BITS._SH15
#define SH26 ICSYS1.ICSYS_BITS._SH26
#define SH37 ICSYS1.ICSYS_BITS._SH37
/*******************************************************************************************/
/* TIMER TEST REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char BIT0:1;
unsigned char _TCBYP:1;
unsigned char BIT2:1;
unsigned char BIT3:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char BIT6:1;
unsigned char BIT7:1;
} TIMTST_BITS;
unsigned char TIMTST_BYTE;
} TIMTST1 _IO_AT(0x6D);
/*DEFINE REGISTER*/
#define TIMTST TIMTST1.TIMTST_BYTE
/*DEFINE REGISTER BITS*/
#define TCBBYP TIMTST1.TIMTST_BITS._TCBYP
/*******************************************************************************************/
/* 16-BIT PULSE ACCUMULATOR B CONTROL REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char BIT0:1;
unsigned char _PB0VI:1;
unsigned char BIT2:1;
unsigned char BIT3:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char _PBEN:1;
unsigned char BIT7:1;
} PBCTL_BITS;
unsigned char PBCTL_BYTE;
} PBCTL1 _IO_AT(0x70);
/*DEFINE REGISTER*/
#define PBCTL PBCTL1.PBCTL_BYTE
/*DEFINE REGISTER BITS*/
#define PB0VI PBCTL1.PBCTL_BITS._PB0VI
#define PBEN PBCTL1.PBCTL_BITS._PBEN
/*******************************************************************************************/
/* 16-BIT PULSE ACCUMULATOR B FLAG REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char BIT0:1;
unsigned char _PB0VF:1;
unsigned char BIT2:1;
unsigned char BIT3:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char BIT6:1;
unsigned char BIT7:1;
} PBFLG_BITS;
unsigned char PBFLG_BYTE;
} PBFLG1 _IO_AT(0x71);
/*DEFINE REGISTER*/
#define PBFLG PBFLG1.PBFLG_BYTE
/*DEFINE REGISTER BITS*/
#define PB0VF PBFLG1.PBFLG_BITS._PB0VF
/*******************************************************************************************/
/* 8-BIT PULSE ACCUMULATORS HOLDING REGISTERS */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile unsigned char PA3H _IO_AT(0x72);
__DECL__6812DP256_H__ vol⌨️ 快捷键说明
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