📄 6812dp256.h
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#define COPBYP FORBYP1.FORBYP_BITS._COPBYP
#define RTIBYP FORBYP1.FORBYP_BITS._RTIBYP
/**************************************************************************************************/
/* */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile unsigned char CTCTL _IO_AT(0x3E);
__DECL__6812DP256_H__ volatile unsigned char ARMCOP _IO_AT(0x3F);
/*******************************************************************************************/
/* TIMER INPUT/OUTPUT COMPARE SELECT */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile unsigned char TIOS _IO_AT(0x40);
/*******************************************************************************************/
/* TIMER COMPARE FORCE REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile unsigned char CFORC _IO_AT(0x41);
#define TCFORC CFORC /* Motorola documentation is inconsistent (CFORC and TCFORC used) */
/*******************************************************************************************/
/* OUTPUT COMPARE 7 MASK REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile unsigned char OC7M _IO_AT(0x42);
#define TOC7M OC7M /* Motorola documentation is inconsistent (TOC7M and OC7M used) */
/*******************************************************************************************/
/* OUTPUT COMPARE 7 DATA REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile unsigned char OC7D _IO_AT(0x43);
#define TOC7D OC7D /* Motorola documentation is inconsistent (TOC7D and OC7D used) */
/*******************************************************************************************/
/* OUTPUT COMPARE 7 DATA REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile unsigned int TCNT _IO_AT(0x44);
/*******************************************************************************************/
/* TIMER SYSTEM CONTROL REGISTER 1 */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char BIT0:1;
unsigned char BIT1:1;
unsigned char BIT2:1;
unsigned char BIT3:1;
unsigned char _TFFCA:1;
unsigned char _TSFRZ:1;
unsigned char _TSWAI:1;
unsigned char _TEN:1;
} TSCR1_BITS;
unsigned char TSCR1_BYTE;
} TSCR11 _IO_AT(0x46);
/*DEFINE REGISTER*/
#define TSCR1 TSCR11.TSCR1_BYTE
/*DEFINE REGISTER BITS*/
#define TFFCA TSCR11.TSCR1_BITS._TFFCA
#define TSFRZ TSCR11.TSCR1_BITS._TSFRZ
#define TSWAI TSCR11.TSCR1_BITS._TSWAI
#define TEN TSCR11.TSCR1_BITS._TEN
/*******************************************************************************************/
/* */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile unsigned char TTOV _IO_AT(0x47);
/*******************************************************************************************/
/* TIMER CONTROL REGISTER 1 */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _OL4:1;
unsigned char _OM4:1;
unsigned char _OL5:1;
unsigned char _OM5:1;
unsigned char _OL6:1;
unsigned char _OM6:1;
unsigned char _OL7:1;
unsigned char _OM7:1;
} TCTL1_BITS;
unsigned char TCTL1_BYTE;
} TCTL11 _IO_AT(0x48);
/*DEFINE REGISTER*/
#define TCTL1 TCTL11.TCTL1_BYTE
/*DEFINE REGISTER BITS*/
#define OL4 TCTL11.TCTL1_BITS._OL4
#define OM4 TCTL11.TCTL1_BITS._OM4
#define OL5 TCTL11.TCTL1_BITS._OL5
#define OM5 TCTL11.TCTL1_BITS._OM5
#define OL6 TCTL11.TCTL1_BITS._OL6
#define OM6 TCTL11.TCTL1_BITS._OM6
#define OL7 TCTL11.TCTL1_BITS._OL7
#define OM7 TCTL11.TCTL1_BITS._OM7
/*******************************************************************************************/
/* TIMER CONTROL REGISTER 2 */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _OL0:1;
unsigned char _OM0:1;
unsigned char _OL1:1;
unsigned char _OM1:1;
unsigned char _OL2:1;
unsigned char _OM2:1;
unsigned char _OL3:1;
unsigned char _OM3:1;
} TCTL2_BITS;
unsigned char TCTL2_BYTE;
} TCTL21 _IO_AT(0x49);
/*DEFINE REGISTER*/
#define TCTL2 TCTL21.TCTL2_BYTE
/*DEFINE REGISTER BITS*/
#define OL0 TCTL21.TCTL2_BITS._OL0
#define OM0 TCTL21.TCTL2_BITS._OM0
#define OL1 TCTL21.TCTL2_BITS._OL1
#define OM1 TCTL21.TCTL2_BITS._OM1
#define OL2 TCTL21.TCTL2_BITS._OL2
#define OM2 TCTL21.TCTL2_BITS._OM2
#define OL3 TCTL21.TCTL2_BITS._OL3
#define OM3 TCTL21.TCTL2_BITS._OM3
/*******************************************************************************************/
/* TIMER CONTROL REGISTER 3 */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _EDG4A:1;
unsigned char _EDG4B:1;
unsigned char _EDG5A:1;
unsigned char _EDG5B:1;
unsigned char _EDG6A:1;
unsigned char _EDG6B:1;
unsigned char _EDG7A:1;
unsigned char _EDG7B:1;
} TCTL3_BITS;
unsigned char TCTL3_BYTE;
} TCTL31 _IO_AT(0x4A);
/*DEFINE REGISTER*/
#define TCTL3 TCTL31.TCTL3_BYTE
/*DEFINE REGISTER BITS*/
#define EDG4A TCTL31.TCTL3_BITS._EDG4A
#define EDG4B TCTL31.TCTL3_BITS._EDG4B
#define EDG5A TCTL31.TCTL3_BITS._EDG5A
#define EDG5B TCTL31.TCTL3_BITS._EDG5B
#define EDG6A TCTL31.TCTL3_BITS._EDG6A
#define EDG6B TCTL31.TCTL3_BITS._EDG6B
#define EDG7A TCTL31.TCTL3_BITS._EDG7A
#define EDG7B TCTL31.TCTL3_BITS._EDG7B
/*******************************************************************************************/
/* TIMER CONTROL REGISTER 4 */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _EDG0A:1;
unsigned char _EDG0B:1;
unsigned char _EDG1A:1;
unsigned char _EDG1B:1;
unsigned char _EDG2A:1;
unsigned char _EDG2B:1;
unsigned char _EDG3A:1;
unsigned char _EDG3B:1;
} TCTL4_BITS;
unsigned char TCTL4_BYTE;
} TCTL41 _IO_AT(0x4B);
/*DEFINE REGISTER*/
#define TCTL4 TCTL41.TCTL4_BYTE
/*DEFINE REGISTER BITS*/
#define EDG0A TCTL41.TCTL4_BITS._EDG0A
#define EDG0B TCTL41.TCTL4_BITS._EDG0B
#define EDG1A TCTL41.TCTL4_BITS._EDG1A
#define EDG1B TCTL41.TCTL4_BITS._EDG1B
#define EDG2A TCTL41.TCTL4_BITS._EDG2A
#define EDG2B TCTL41.TCTL4_BITS._EDG2B
#define EDG3A TCTL41.TCTL4_BITS._EDG3A
#define EDG3B TCTL41.TCTL4_BITS._EDG3B
/*******************************************************************************************/
/* TIMER INTERRUPT ENABLE REGISTER */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _C0I:1;
unsigned char _C1I:1;
unsigned char _C2I:1;
unsigned char _C3I:1;
unsigned char _C4I:1;
unsigned char _C5I:1;
unsigned char _C6I:1;
unsigned char _C7I:1;
} TIE_BITS;
unsigned char TIE_BYTE;
} _TIE _IO_AT(0x4C);
/*DEFINE REGISTER*/
#define TIE _TIE.TIE_BYTE
/*DEFINE REGISTER BITS*/
#define C0I _TIE.TIE_BITS._C0I
#define C1I _TIE.TIE_BITS._C1I
#define C2I _TIE.TIE_BITS._C2I
#define C3I _TIE.TIE_BITS._C3I
#define C4I _TIE.TIE_BITS._C4I
#define C5I _TIE.TIE_BITS._C5I
#define C6I _TIE.TIE_BITS._C6I
#define C7I _TIE.TIE_BITS._C7I
/*******************************************************************************************/
/* TIMER SYSTEM CONTROL REGISTER 2 */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _PR0:1;
unsigned char _PR1:1;
unsigned char _PR2:1;
unsigned char _TCRE:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char BIT6:1;
unsigned char _TOI:1;
} TSCR2_BITS;
unsigned char TSCR2_BYTE;
} TSCR21 _IO_AT(0x4D);
/*DEFINE REGISTER*/
#define TSCR2 TSCR21.TSCR2_BYTE
/*DEFINE REGISTER BITS*/
#define PR0 TSCR21.TSCR2_BITS._PR0
#define PR1 TSCR21.TSCR2_BITS._PR1
#define PR2 TSCR21.TSCR2_BITS._PR2
#define TCRE TSCR21.TSCR2_BITS._TCRE
#define TOI TSCR21.TSCR2_BITS._TOI
/*******************************************************************************************/
/* TIMER INTERRUPT FLAG 1 */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _C0F:1;
unsigned char _C1F:1;
unsigned char _C2F:1;
unsigned char _C3F:1;
unsigned char _C4F:1;
unsigned char _C5F:1;
unsigned char _C6F:1;
unsigned char _C7F:1;
} TFLG1_BITS;
unsigned char TFLG1_BYTE;
} TFLG11 _IO_AT(0x4E);
/*DEFINE REGISTER*/
#define TFLG1 TFLG11.TFLG1_BYTE
/*DEFINE REGISTER BITS*/
#define C0F TFLG11.TFLG1_BITS._C0F
#define C1F TFLG11.TFLG1_BITS._C1F
#define C2F TFLG11.TFLG1_BITS._C2F
#define C3F TFLG11.TFLG1_BITS._C3F
#define C4F TFLG11.TFLG1_BITS._C4F
#define C5F TFLG11.TFLG1_BITS._C5F
#define C6F TFLG11.TFLG1_BITS._C6F
#define C7F TFLG11.TFLG1_BITS._C7F
/*******************************************************************************************/
/* TIMER INTERRUPT FLAG 2 */
/*******************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char BIT0:1;
unsigned char BIT1:1;
unsigned char BIT2:1;
unsigned char BIT3:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char BIT6:1;
unsigned char _TOF:1;
} TFLG2_BITS;
unsigned char TFLG2_BYTE;
} TFLG21 _IO_AT(0x4F);
/*DEFINE REGISTER*/
#define TFLG2 TFLG21.TFLG2_BYTE
/*DEFINE REGISTER BITS*/
#define TOF TFLG21.TFLG2_BITS._TOF
/*******************************************************************************************/
/* TIMER INPUT CAPTURE/OUTPUT REGISTERS */
/*******************************************************************************************/
/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 0*****/
__DECL__6812DP256_H__ volatile unsigned int TC0 _IO_AT(0x50);
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