📄 6812dp256.h
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/* EXTERNAL BUS INTERFACE CONTROL */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _ESTR:1;
unsigned char BIT1:1;
unsigned char BIT2:1;
unsigned char BIT3:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char BIT6:1;
unsigned char BIT7:1;
} EBICTL_BITS;
unsigned char EBICTL_BYTE;
}EBICTL1 _IO_AT(0x0E);
/*DEFINE REGISTER*/
#define EBICTL EBICTL1.EBICTL_BYTE
/*DEFINE REGISTER BITS*/
#define ESTR EBICTL1.EBICTL_BITS._ESTR
/**************************************************************************************************/
/* INITIALIZATION OF INTERNAL RAM POSITION REGISTER */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _RAMHAL:1;
unsigned char BIT1:1;
unsigned char BIT2:1;
unsigned char _RAM11:1;
unsigned char _RAM12:1;
unsigned char _RAM13:1;
unsigned char _RAM14:1;
unsigned char _RAM15:1;
} INITRM_BITS;
unsigned char INITRM_BYTE;
}INITRM1 _IO_AT(0x10);
/*DEFINE REGISTER*/
#define INITRM INITRM1.INITRM_BYTE
/*DEFINE REGISTER BITS*/
#define RAMHAL INITRM1.INITRM_BITS._RAMHAL
#define RAM11 INITRM1.INITRM_BITS._RAM11
#define RAM12 INITRM1.INITRM_BITS._RAM12
#define RAM13 INITRM1.INITRM_BITS._RAM13
#define RAM14 INITRM1.INITRM_BITS._RAM14
#define RAM15 INITRM1.INITRM_BITS._RAM15
/**************************************************************************************************/
/* INITIALIZATION OF INTERNAL REGISTER POSITION REGISTER */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char BIT0:1;
unsigned char BIT1:1;
unsigned char BIT2:1;
unsigned char _REG11:1;
unsigned char _REG12:1;
unsigned char _REG13:1;
unsigned char _REG14:1;
unsigned char _REG15:1;
} INITRG_BITS;
unsigned char INITRG_BYTE;
}INITRG1 _IO_AT(0x11);
/*DEFINE REGISTER*/
#define INITRG INITRG1.INITRG_BYTE
/*DEFINE REGISTER BITS*/
#define REG11 INITRG1.INITRG_BITS._REG11
#define REG12 INITRG1.INITRG_BITS._REG12
#define REG13 INITRG1.INITRG_BITS._REG13
#define REG14 INITRG1.INITRG_BITS._REG14
#define REG15 INITRG1.INITRG_BITS._REG15
/**************************************************************************************************/
/* INITIALIZATION OF INTERNAL EEPROM POSITION REGISTER */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _EEON:1;
unsigned char BIT1:1;
unsigned char BIT2:1;
unsigned char BIT3:1;
unsigned char _EE12:1;
unsigned char _EE13:1;
unsigned char _EE14:1;
unsigned char _EE15:1;
} INITEE_BITS;
unsigned char INITEE_BYTE;
}INITEE1 _IO_AT(0x12);
/*DEFINE REGISTER*/
#define INITEE INITEE1.INITEE_BYTE
/*DEFINE REGISTER BITS*/
#define EEON INITEE1.INITEE_BITS._EEON
#define EE12 INITEE1.INITEE_BITS._EE12
#define EE13 INITEE1.INITEE_BITS._EE13
#define EE14 INITEE1.INITEE_BITS._EE14
#define EE15 INITEE1.INITEE_BITS._EE15
/**************************************************************************************************/
/* MISCELLANEOUS MAPPING CONTROL REGISTER */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _ROMON:1;
unsigned char _ROMHM:1;
unsigned char _EXSTR0:1;
unsigned char _EXSTR1:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char BIT6:1;
unsigned char BIT7:1;
} MISC_BITS;
unsigned char MISC_BYTE;
}MISC1 _IO_AT(0x13);
/*DEFINE REGISTER*/
#define MISC MISC1.MISC_BYTE
/*DEFINE REGISTER BITS*/
#define ROMON MISC1.MISC_BITS._ROMON
#define ROMHM MISC1.MISC_BITS._ROMHM
#define EXSTR0 MISC1.MISC_BITS._EXSTR0
#define EXSTR1 MISC1.MISC_BITS._EXSTR1
/**************************************************************************************************/
/* MAPPING TEST REGISTERS */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile unsigned char MTST0 _IO_AT(0x14);
__DECL__6812DP256_H__ volatile unsigned char MTST1 _IO_AT(0x17);
/**************************************************************************************************/
/* INTERRUPT TEST CONTROL REGISTER */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _ADR0:1;
unsigned char _ADR1:1;
unsigned char _ADR2:1;
unsigned char _ADR3:1;
unsigned char _WRINT:1;
unsigned char BIT5:1;
unsigned char BIT6:1;
unsigned char BIT7:1;
} ITCR_BITS;
unsigned char ITCR_BYTE;
}ITCR1 _IO_AT(0x15);
/*DEFINE REGISTER*/
#define ITCR ITCR1.ITCR_BYTE
/*DEFINE REGISTER BITS*/
#define ADR0 ITCR1.ITCR_BITS._ADR0
#define ADR1 ITCR1.ITCR_BITS._ADR1
#define ADR2 ITCR1.ITCR_BITS._ADR2
#define ADR3 ITCR1.ITCR_BITS._ADR3
#define WRINT ITCR1.ITCR_BITS._WRINT
/**************************************************************************************************/
/* INTERRUPT TEST REGISTER */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _INT0:1;
unsigned char _INT2:1;
unsigned char _INT4:1;
unsigned char _INT6:1;
unsigned char _INT8:1;
unsigned char _INTA:1;
unsigned char _INTC:1;
unsigned char _INTE:1;
} ITEST_BITS;
unsigned char ITEST_BYTE;
}ITEST1 _IO_AT(0x16);
/*DEFINE REGISTER*/
#define ITEST ITEST1.ITEST_BYTE
/*DEFINE REGISTER BITS*/
#define INT0 ITEST1.ITEST_BITS._INT0
#define INT2 ITEST1.ITEST_BITS._INT2
#define INT4 ITEST1.ITEST_BITS._INT4
#define INT6 ITEST1.ITEST_BITS._INT6
#define INT8 ITEST1.ITEST_BITS._INT8
#define INTA ITEST1.ITEST_BITS._INTA
#define INTC ITEST1.ITEST_BITS._INTC
#define INTE ITEST1.ITEST_BITS._INTE
/**************************************************************************************************/
/* PART ID REGISTER ASSIGNMENTS */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _PARTIDH;
unsigned char _PARTIDL;
} PARTID_BYTES;
unsigned int PARTID_WORD;
}PARTID1 _IO_AT(0x1A);
/*DEFINE REGISTER*/
#define PARTID PARTID1.PARTID_WORD
/*DEFINE REGISTER BYTES*/
#define PARTIDH PARTID1.PARTID_BYTES._PARTIDH
#define PARTIDL PARTID1.PARTID_BYTES._PARTIDL
/**************************************************************************************************/
/* */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _ram_sw0:1;
unsigned char _ram_sw1:1;
unsigned char _ram_sw2:1;
unsigned char BIT3:1;
unsigned char _eep_sw0:1;
unsigned char _eep_sw1:1;
unsigned char BIT6:1;
unsigned char _reg_sw0:1;
} MEMSIZ0_BITS;
unsigned char MEMSIZ0_BYTE;
}MEMSIZ01 _IO_AT(0x1C);
/*DEFINE REGISTER*/
#define MEMSIZ0 MEMSIZ01.MEMSIZ0_BYTE
/*DEFINE REGISTER BITS*/
#define ram_sw0 MEMSIZ01.MEMSIZ0_BITS._ram_sw0
#define ram_sw1 MEMSIZ01.MEMSIZ0_BITS._ram_sw1
#define ram_sw2 MEMSIZ01.MEMSIZ0_BITS._ram_sw2
#define eep_sw0 MEMSIZ01.MEMSIZ0_BITS._eep_sw0
#define eep_sw1 MEMSIZ01.MEMSIZ0_BITS._eep_sw1
#define reg_sw0 MEMSIZ01.MEMSIZ0_BITS._reg_sw0
/**************************************************************************************************/
/* */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char _pag_sw0:1;
unsigned char _pag_sw1:1;
unsigned char BIT2:1;
unsigned char BIT3:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char _rom_sw0:1;
unsigned char _rom_sw1:1;
} MEMSIZ1_BITS;
unsigned char MEMSIZ1_BYTE;
}MEMSIZ11 _IO_AT(0x1D);
/*DEFINE REGISTER*/
#define MEMSIZ1 MEMSIZ11.MEMSIZ1_BYTE
/*DEFINE REGISTER BITS*/
#define pag_sw0 MEMSIZ11.MEMSIZ1_BITS._pag_sw0
#define pag_sw1 MEMSIZ11.MEMSIZ1_BITS._pag_sw1
#define rom_sw0 MEMSIZ11.MEMSIZ1_BITS._rom_sw0
#define rom_sw1 MEMSIZ11.MEMSIZ1_BITS._rom_sw1
/**************************************************************************************************/
/* INTERRUPT CONTROL REGISTER */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char BIT0:1;
unsigned char BIT1:1;
unsigned char BIT2:1;
unsigned char BIT3:1;
unsigned char BIT4:1;
unsigned char BIT5:1;
unsigned char _IRQEN:1;
unsigned char _IRQE:1;
} INTCR_BITS;
unsigned char INTCR_BYTE;
}INTCR1 _IO_AT(0x1E);
/*DEFINE REGISTER*/
#define INTCR INTCR1.INTCR_BYTE
/*DEFINE REGISTER BITS*/
#define IRQEN INTCR1.INTCR_BITS._IRQEN
#define IRQE INTCR1.INTCR_BITS._IRQE
/**************************************************************************************************/
/* HIGHEST PRIORITY I INTERRUPT */
/**************************************************************************************************/
__DECL__6812DP256_H__ volatile union {
struct {
unsigned char BIT0:1;
unsigned char _PSEL1:1;
unsigned char _PSEL2:1;
unsigned char _PSEL3:1;
unsigned char _PSEL4:1;
unsigned char _PSEL5:1;
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