vhdl延时10s.txt

开发环境是FPGA开发工具

如果输入信号不是四线，需作适当修改；



-- 系统时钟不是1Hz，需分频获得1Hz；



-- 程序功能：屏蔽头10秒信号



library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity delay10s is
   port(clk_1Hz    :in std_logic;  -- 秒
       data_in    :in std_logic_vector(3 downto 0);    -- 输入信号，设为四线
       data_out   :out std_logic_vector(3 downto 0));   -- 输出信号
end delay10s;
architecture arch of delay10s is
  signal count:integer range 0 to 16;
begin
  process(clk_1Hz)
begin
   if clk_1Hz'event and clk_1Hz='1' then
   if count>=10 then
    count<=count;
        else
    count <= count+1;
   
    end if;

    end if;

end process;

process(count)

begin
 case count is

  when 0 to 9 =>

   data_out<="ZZZZ";

    when others =>
data_out<=data_in;



      end case;
end process;
end arch;