📄 gpif1.lst
字号:
181 /* LenBr */ 0x08, 0x03, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x07,
182 /* Opcode*/ 0x01, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
183 /* Output*/ 0xDF, 0xDD, 0xDF, 0xDF, 0xDF, 0xDF, 0xDF, 0xDB,
184 /* LFun */ 0x09, 0x09, 0x12, 0x12, 0x00, 0x2D, 0x36, 0x3F
185 };
186 // END DO NOT EDIT
187
188 // DO NOT EDIT ...
189 const char xdata InitData[7] =
190 {
191 /* Regs */ 0xA0,0x00,0x00,0xDB,0x06,0xE4,0x31
192 };
193 // END DO NOT EDIT
194
195 // TO DO: You may add additional code below.
196
197 void GpifInit( void )
198 {
199 1 BYTE i;
200 1
201 1 // Registers which require a synchronization delay, see section 15.14
202 1 // FIFORESET FIFOPINPOLAR
203 1 // INPKTEND OUTPKTEND
204 1 // EPxBCH:L REVCTL
205 1 // GPIFTCB3 GPIFTCB2
206 1 // GPIFTCB1 GPIFTCB0
207 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
208 1 // EPxFIFOCFG EPxGPIFFLGSEL
209 1 // PINFLAGSxx EPxFIFOIRQ
210 1 // EPxFIFOIE GPIFIRQ
211 1 // GPIFIE GPIFADRH:L
212 1 // UDMACRCH:L EPxGPIFTRIG
213 1 // GPIFTRIG
214 1
215 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
216 1 // ...these have been replaced by GPIFTC[B3:B0] registers
217 1
218 1 // 8051 doesn't have access to waveform memories 'til
219 1 // the part is in GPIF mode.
220 1
221 1 IFCONFIG = 0xCA;
222 1 // IFCLKSRC=1 , FIFOs executes on internal clk source
223 1 // xMHz=1 , 48MHz internal clk rate
224 1 // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
225 1 // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
226 1 // ASYNC=1 , master samples asynchronous
227 1 // GSTATE=0 , Drive GPIF states out on PORTE[2:0], debug WF
228 1 // IFCFG[1:0]=10, FX2 in GPIF master mode
229 1
230 1 GPIFABORT = 0xFF; // abort any waveforms pending
231 1
232 1 GPIFREADYCFG = InitData[ 0 ];
233 1 GPIFCTLCFG = InitData[ 1 ];
234 1 GPIFIDLECS = InitData[ 2 ];
235 1 GPIFIDLECTL = InitData[ 3 ];
236 1 GPIFWFSELECT = InitData[ 5 ];
237 1
238 1 // use dual autopointer feature...
239 1 AUTOPTRSETUP = 0x07; // inc both pointers,
240 1 // ...warning: this introduces pdata hole(s)
C51 COMPILER V6.23a GPIF1 10/26/2005 19:02:16 PAGE 5
241 1 // ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
242 1
243 1 // source
244 1 APTR1H = MSB( &WaveData );
245 1 APTR1L = LSB( &WaveData );
246 1
247 1 // destination
248 1 AUTOPTRH2 = 0xE4;
249 1 AUTOPTRL2 = 0x00;
250 1
251 1 // transfer
252 1 for ( i = 0x00; i < 128; i++ )
253 1 {
254 2 EXTAUTODAT2 = EXTAUTODAT1;
255 2 }
256 1
257 1 // Configure GPIF Address pins, output initial value,
258 1 PORTCCFG = 0xFF; // [7:0]=1 as alt. func. GPIFADR[7:0]
259 1 OEC = 0xFF; // and as outputs
260 1 PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
261 1 OEE |= 0x80; // and as output
262 1
263 1 // ...OR... tri-state GPIFADR[8:0] pins
264 1 // PORTCCFG = 0x00; // [7:0] as port I/O
265 1 // OEC = 0x00; // and as inputs
266 1 // PORTECFG &= 0x7F; // [8] as port I/O
267 1 // OEE &= 0x7F; // and as input
268 1
269 1 // GPIF address pins update when GPIFADRH/L written
270 1 SYNCDELAY; //
271 1 GPIFADRH = 0x00; // bits[7:1] always 0
272 1 SYNCDELAY; //
273 1 GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
274 1 }
275
276 //#define TESTING_GPIF // NOTE: Comment this line out for frameworks based firmware
277 // See the example GPIF Tool Utility under Application
278 // Reference Material for more advanced development info
279 #ifdef TESTING_GPIF
// TODO: You may add additional code below.
void OtherInit( void )
{ // interface initialization
// ...see TD_Init( );
}
// Set Address GPIFADR[8:0] to PERIPHERAL
void Peripheral_SetAddress( WORD gaddr )
{
SYNCDELAY; //
GPIFADRH = gaddr >> 8;
SYNCDELAY; //
GPIFADRL = ( BYTE )gaddr; // setup GPIF address
}
// Set EP2GPIF Transaction Count
void Peripheral_SetEP2GPIFTC( WORD xfrcnt )
{
SYNCDELAY; //
EP2GPIFTCH = xfrcnt >> 8; // setup transaction count
SYNCDELAY; //
EP2GPIFTCL = ( BYTE )xfrcnt;
C51 COMPILER V6.23a GPIF1 10/26/2005 19:02:16 PAGE 6
}
// Set EP4GPIF Transaction Count
void Peripheral_SetEP4GPIFTC( WORD xfrcnt )
{
SYNCDELAY; //
EP4GPIFTCH = xfrcnt >> 8; // setup transaction count
SYNCDELAY; //
EP4GPIFTCL = ( BYTE )xfrcnt;
}
// Set EP6GPIF Transaction Count
void Peripheral_SetEP6GPIFTC( WORD xfrcnt )
{
SYNCDELAY; //
EP6GPIFTCH = xfrcnt >> 8; // setup transaction count
SYNCDELAY; //
EP6GPIFTCL = ( BYTE )xfrcnt;
}
// Set EP8GPIF Transaction Count
void Peripheral_SetEP8GPIFTC( WORD xfrcnt )
{
SYNCDELAY; //
EP8GPIFTCH = xfrcnt >> 8; // setup transaction count
SYNCDELAY; //
EP8GPIFTCL = ( BYTE )xfrcnt;
}
#define GPIF_FLGSELPF 0
#define GPIF_FLGSELEF 1
#define GPIF_FLGSELFF 2
// Set EP2GPIF Decision Point FIFO Flag Select (PF, EF, FF)
void SetEP2GPIFFLGSEL( WORD DP_FIFOFlag )
{
EP2GPIFFLGSEL = DP_FIFOFlag;
}
// Set EP4GPIF Decision Point FIFO Flag Select (PF, EF, FF)
void SetEP4GPIFFLGSEL( WORD DP_FIFOFlag )
{
EP4GPIFFLGSEL = DP_FIFOFlag;
}
// Set EP6GPIF Decision Point FIFO Flag Select (PF, EF, FF)
void SetEP6GPIFFLGSEL( WORD DP_FIFOFlag )
{
EP6GPIFFLGSEL = DP_FIFOFlag;
}
// Set EP8GPIF Decision Point FIFO Flag Select (PF, EF, FF)
void SetEP8GPIFFLGSEL( WORD DP_FIFOFlag )
{
EP8GPIFFLGSEL = DP_FIFOFlag;
}
// Set EP2GPIF Programmable Flag STOP, overrides Transaction Count
void SetEP2GPIFPFSTOP( void )
{
EP2GPIFPFSTOP = 0x01;
}
C51 COMPILER V6.23a GPIF1 10/26/2005 19:02:16 PAGE 7
// Set EP4GPIF Programmable Flag STOP, overrides Transaction Count
void SetEP4GPIFPFSTOP( void )
{
EP4GPIFPFSTOP = 0x01;
}
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -