📄 periph.lst
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302 3 {
303 4 // should take <75usec @ 8-bit async.
C51 COMPILER V6.23a PERIPH 10/26/2005 19:02:17 PAGE 6
304 4 ; // poll GPIFTRIG.7, DONE bit...
305 4 }
306 3 // SYNCDELAY;
307 3 // OUTPKTEND = 0x02; // SKIP=0, pass buffer on to master
308 3 // SYNCDELAY;
309 3 IOA = 0xFF;
310 3 COUNT = 0;
311 3 while(COUNT <2)
312 3 {
313 4 COUNT++;
314 4 }
315 3 IOA = 0;
316 3 // IOA = 0x01;
317 3 // ALREADY_READ = FALSE; when selftest
318 3 // signal "shortpkt" to peripheral peripheral here...
319 3 // }
320 3 // else
321 3 // {
322 3 // was max. pkt. size...
323 3 // ...let transaction terminate naturally...
324 3 // }
325 3 }
326 2 }
327 1 // else
328 1 // {
329 1 // DONE=0 when GPIF is "not" IDLE...
330 1 // }
331 1
332 1 /*
333 1 if( GPIFTRIG & 0x80 )
334 1 {
335 1 if( ALREADY_READ == FALSE )
336 1 {
337 1
338 1 if( EP68FIFOFLGS & 0x01 )
339 1 {
340 1 // EP6FF=1, when fifo "full"
341 1
342 1 }
343 1 else
344 1 {
345 1 // EP6FF=0, when fifo "not full", buffer available...
346 1 */
347 1 /*
348 1 DatAddress = CMDADDR;
349 1 Peripheral_SetAddress( DatAddress );
350 1 // setup GPIF transaction count
351 1 SYNCDELAY;
352 1 EP6GPIFTCH = 0x01; //260
353 1 SYNCDELAY;
354 1 EP6GPIFTCL = 0x04;
355 1 SYNCDELAY;
356 1
357 1 // trigger FIFO read transaction(s), using SFR
358 1 // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
359 1 GPIFTRIG = GPIFTRIGRD | GPIF_EP6;
360 1
361 1 // NOTE: 512 bytes transfers in ~75usec on 8-bit async bus
362 1 // NOTE: 64 bytes transfers in ~10usec on 8-bit async bus
363 1
364 1 // wait for the transaction to terminate naturally...
365 1 SYNCDELAY; //
C51 COMPILER V6.23a PERIPH 10/26/2005 19:02:17 PAGE 7
366 1 while( !( GPIFTRIG & 0x80 ) )
367 1 {
368 1 // should take <75usec @ 8-bit async.
369 1 ; // poll GPIFTRIG.7, DONE bit...
370 1 }
371 1
372 1 // AUTOIN=0, so 8051 pass pkt. to host...
373 1 SYNCDELAY; //
374 1 INPKTEND = 0x06; // w/skip=0;.commit however many bytes in pkt.
375 1 SYNCDELAY; //
376 1 // ...NOTE: this also handles "shortpkt"
377 1 */
378 1 /*
379 1 DatAddress = CMDADDR;
380 1 Peripheral_SetAddress( DatAddress );
381 1 // setup GPIF transaction count
382 1 SYNCDELAY;
383 1 EP6GPIFTCH = 0; //260-8=0xFC
384 1 SYNCDELAY;
385 1 EP6GPIFTCL = 0xFC;
386 1 SYNCDELAY;
387 1
388 1 // trigger FIFO read transaction(s), using SFR
389 1 // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
390 1 GPIFTRIG = GPIFTRIGRD | GPIF_EP6;
391 1
392 1 // NOTE: 512 bytes transfers in ~75usec on 8-bit async bus
393 1 // NOTE: 64 bytes transfers in ~10usec on 8-bit async bus
394 1
395 1 // wait for the transaction to terminate naturally...
396 1 SYNCDELAY; //
397 1 while( !( GPIFTRIG & 0x80 ) )
398 1 {
399 1 // should take <75usec @ 8-bit async.
400 1 ; // poll GPIFTRIG.7, DONE bit...
401 1 }
402 1 // DEAL WITH THE HIGH 8 BYTES
403 1 GPIFWFSELECT = 0xC6; //EIGHT BYTE READ EXCHANG FIFOREAD
404 1 DatAddress = 0xf0fe;
405 1 Peripheral_SetAddress( DatAddress );
406 1 // setup GPIF transaction count
407 1 SYNCDELAY;
408 1 EP6GPIFTCH = 0;
409 1 SYNCDELAY;
410 1 EP6GPIFTCL = 0x08;
411 1 SYNCDELAY;
412 1
413 1 // trigger FIFO read transaction(s), using SFR
414 1 // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
415 1 GPIFTRIG = GPIFTRIGRD | GPIF_EP6;
416 1
417 1 // wait for the transaction to terminate naturally...
418 1 SYNCDELAY; //
419 1 while( !( GPIFTRIG & 0x80 ) )
420 1 {
421 1 // should take <75usec @ 8-bit async.
422 1 ; // poll GPIFTRIG.7, DONE bit...
423 1 }
424 1 GPIFWFSELECT = 0xE4; //INITIAL WAVEFORM
425 1
426 1 // EP6FIFOBUF[ 0 ] = REVID; //
427 1 // SYNCDELAY;
C51 COMPILER V6.23a PERIPH 10/26/2005 19:02:17 PAGE 8
428 1 // EP6BCH = 0x00;
429 1 // SYNCDELAY;
430 1 // EP6BCL = 0x01; // pass src’d buffer on to host
431 1
432 1 // AUTOIN=0, so 8051 pass pkt. to host...
433 1 SYNCDELAY; //
434 1 INPKTEND = 0x06; // w/skip=0;.commit however many bytes in pkt.
435 1 SYNCDELAY; //
436 1 // ...NOTE: this also handles "shortpkt"
437 1 ALREADY_READ = TRUE;
438 1 }
439 1 }
440 1 }
441 1 */
442 1 if( cishu > 0x03E8 )
443 1 {
444 2 cishu = 0;
445 2 IOA = 0xFF;
446 2 COUNT = 0;
447 2 while(COUNT <2)
448 2 {
449 3 COUNT++;
450 3 }
451 2 IOA = 0;
452 2 }
453 1 // Handle IN data...
454 1 // is the peripheral interface idle...
455 1 if( GPIFTRIG & 0x80 )
456 1 {
457 2
458 2 if( GPIFREADYSTAT & 0x01 )
459 2 {
460 3 // RDY0=1, LOW AREA DATA IS OK.
461 3 if (Flag_Of_DataHI == TRUE)
462 3 {
463 4 if( EP68FIFOFLGS & 0x01 )
464 4 {
465 5 // EP6FF=1, when fifo "full"
466 5 }
467 4 else
468 4 {
469 5 cishu++;
470 5 // IOA = 0;
471 5 // EP6FF=0, when fifo "not full", buffer available...
472 5 SYNCDELAY;
473 5 GPIFWFSELECT = 0xE4; //INITIAL WAVEFORM added at 10.06
474 5 //DatAddress = DLADDR;
475 5 //Peripheral_SetAddress( DatAddress );
476 5 SYNCDELAY; //
477 5 GPIFADRH = 0x00;
478 5 SYNCDELAY; // added at 10.06
479 5 GPIFADRL = 0x00; // setup GPIF address
480 5 // setup GPIF transaction count
481 5 SYNCDELAY;
482 5 // EP6GPIFTCH = 0x01;
483 5 EP6GPIFTCH = 0x02;
484 5 SYNCDELAY;
485 5 // EP6GPIFTCL = 0x04;
486 5 EP6GPIFTCL = 0x00;
487 5 // modify 10.06
488 5 SYNCDELAY;
489 5
C51 COMPILER V6.23a PERIPH 10/26/2005 19:02:17 PAGE 9
490 5 // trigger FIFO read transaction(s), using SFR
491 5 // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
492 5 GPIFTRIG = GPIFTRIGRD | GPIF_EP6;
493 5
494 5 // NOTE: 512 bytes transfers in ~75usec on 8-bit async bus
495 5 // NOTE: 64 bytes transfers in ~10usec on 8-bit async bus
496 5
497 5 // wait for the transaction to terminate naturally...
498 5 SYNCDELAY; //
499 5 while( !( GPIFTRIG & 0x80 ) )
500 5 {
501 6 // should take <75usec @ 8-bit async.
502 6 ; // poll GPIFTRIG.7, DONE bit...
503 6 }
504 5
505 5 // AUTOIN=0, so 8051 pass pkt. to host...
506 5 SYNCDELAY; //
507 5 INPKTEND = 0x06; // w/skip=0;.commit however many bytes in pkt.
508 5 SYNCDELAY; //
509 5 // ...NOTE: this also handles "shortpkt"
510 5 Flag_Of_DataHI = FALSE;
511 5
512 5 }
513 4 }
514 3 }
515 2 else
516 2 {
517 3 //RDY0=0:HIGH AREA DATA IS OK.
518 3 if (Flag_Of_DataHI == FALSE)
519 3 {
520 4 if( EP68FIFOFLGS & 0x01 )
521 4 {
522 5 // EP6FF=1, when fifo "full"
523 5
524 5 }
525 4 else
526 4 {
527 5 cishu++;
528 5 // IOA = 0;
529 5 // EP6FF=0, when fifo "not full", buffer available...
530 5 SYNCDELAY;
531 5 GPIFWFSELECT = 0xC6; //EXCHANG FIFOREAD added at 10.06
532 5
533 5 //DatAddress = DHADDR;
534 5 //Peripheral_SetAddress( DatAddress );
535 5 SYNCDELAY; //
536 5 GPIFADRH = 0x00;
537 5 SYNCDELAY; // added at 10.06
538 5 GPIFADRL = 0x00; // setup GPIF address
539 5 // setup GPIF transaction count
540 5 SYNCDELAY;
541 5 // EP6GPIFTCH = 0; //260-8=0xFC
542 5 EP6GPIFTCH = 0x02; //512
543 5 SYNCDELAY;
544 5 // EP6GPIFTCL = 0xFC;
545 5 EP6GPIFTCL = 0x00;
546 5 // modify 10.06
547 5 SYNCDELAY;
548 5
549 5 // trigger FIFO read transaction(s), using SFR
550 5 // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
551 5 GPIFTRIG = GPIFTRIGRD | GPIF_EP6;
C51 COMPILER V6.23a PERIPH 10/26/2005 19:02:17 PAGE 10
552 5
553 5 // NOTE: 512 bytes transfers in ~75usec on 8-bit async bus
554 5 // NOTE: 64 bytes transfers in ~10usec on 8-bit async bus
555 5
556 5 // wait for the transaction to terminate naturally...
557 5 SYNCDELAY; //
558 5 while( !( GPIFTRIG & 0x80 ) )
559 5 {
560 6 // should take <75usec @ 8-bit async.
561 6 ; // poll GPIFTRIG.7, DONE bit...
562 6 }
563 5 // SYNCDELAY;
564 5 // GPIFWFSELECT = 0xE4; //INITIAL WAVEFORM added at 10.06
565 5 /* // DEAL WITH THE HIGH 8 BYTES
566 5 GPIFWFSELECT = 0xC6; //EIGHT BYTE READ EXCHANG FIFOREAD
567 5 DatAddress = DHADDR_8;
568 5 Peripheral_SetAddress( DatAddress );
569 5 // setup GPIF transaction count
570 5 SYNCDELAY;
571 5 EP6GPIFTCH = 0;
572 5 SYNCDELAY;
573 5 EP6GPIFTCL = 0x08;
574 5 SYNCDELAY;
575 5
576 5 // trigger FIFO read transaction(s), using SFR
577 5 // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
578 5 GPIFTRIG = GPIFTRIGRD | GPIF_EP6;
579 5
580 5 // wait for the transaction to terminate naturally...
581 5 SYNCDELAY; //
582 5 while( !( GPIFTRIG & 0x80 ) )
583 5 {
584 5 // should take <75usec @ 8-bit async.
585 5 ; // poll GPIFTRIG.7, DONE bit...
586 5 }
587 5 GPIFWFSELECT = 0xE4; //INITIAL WAVEFORM
588 5 */
589 5 // modify 10.06
590 5 // EP6FIFOBUF[ 0 ] = REVID; //
591 5 // SYNCDELAY;
592 5 // EP6BCH = 0x00;
593 5 // SYNCDELAY;
594 5 // EP6BCL = 0x01; // pass src’d buffer on to host
595 5
596 5 // AUTOIN=0, so 8051 pass pkt. to host...
597 5 SYNCDELAY; //
598 5 INPKTEND = 0x06; // w/skip=0;.commit however many bytes in pkt.
599 5 SYNCDELAY; //
600 5 // ...NOTE: this also handles "shortpkt"
601 5 Flag_Of_DataHI = TRUE;
602 5
603 5 }
604 4 }
605 3
606 3 }
607 2 }
608 1 // else
609 1 // {
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