📄 periph.lst
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C51 COMPILER V6.23a PERIPH 10/26/2005 19:02:17 PAGE 1
C51 COMPILER V6.23a, COMPILATION OF MODULE PERIPH
OBJECT MODULE PLACED IN periph.OBJ
COMPILER INVOKED BY: D:\Keilc623\C51\BIN\C51.EXE periph.c OPTIMIZE(6,SPEED) DEBUG OBJECTEXTEND
stmt level source
1 #pragma NOIV // Do not generate interrupt vectors
2 //-----------------------------------------------------------------------------
3 // File: periph.c
4 // Contents: Hooks required to implement USB peripheral function.
5 //
6 // Copyright (c) 1997 AnchorChips, Inc. All rights reserved
7 //-----------------------------------------------------------------------------
8 #include "fx2.h"
9 #include "fx2regs.h"
10 #include "fx2sdly.h" // SYNCDELAY macro
11
12 extern BOOL GotSUD; // Received setup data flag
13 extern BOOL Sleep;
14 extern BOOL Rwuen;
15 extern BOOL Selfpwr;
16
17 BYTE Configuration; // Current configuration
18 BYTE AlternateSetting; // Alternate settings
19
20 #define DLADDR 0x0400 //Low data area start address
21 //#define DHADDR 0xf504 //High data area start address
22 //#define DHADDR_8 0xf600 //HIGHEST EIGHT DATA AREA SRART ADDRESS
23 #define DHADDR 0x0600 //High data area start address
24 //modify 10.06
25 #define CMDADDR 0x0002 //Command area start address
26
27 #define GPIF_FLGSELPF 0
28 #define GPIF_FLGSELEF 1
29 #define GPIF_FLGSELFF 2
30 #define GPIFTRIGWR 0
31 #define GPIFTRIGRD 4
32 #define GPIF_EP2 0
33 #define GPIF_EP4 1
34 #define GPIF_EP6 2
35 #define GPIF_EP8 3
36
37 // 512 for high speed, 64 for full speed
38 static WORD enum_pkt_size = 0x0000;
39 BOOL Flag_Of_Command; // Store command status
40 //WORD CmdLength = 0; // Command length
41 //WORD CmdAddress; // Current command Address
42 BOOL Flag_Of_DataHI; // Store last data area
43 BOOL FIRSTENTRY; // First Entry
44 BYTE FLAG_ENTRY;
45 int COUNT;
46 int cishu;
47 //BYTE ALREADY_READ; //WHEN selftest
48 // proto's from "gpif.c"
49 void GpifInit( void );
50
51 // Set Address GPIFADR[8:0] to PERIPHERAL
52 void Peripheral_SetAddress( WORD gaddr )
53 {
54 1 SYNCDELAY; //
55 1 GPIFADRH = gaddr >> 8;
C51 COMPILER V6.23a PERIPH 10/26/2005 19:02:17 PAGE 2
56 1 SYNCDELAY; //
57 1 GPIFADRL = ( BYTE )gaddr; // setup GPIF address
58 1 }
59
60
61 //-----------------------------------------------------------------------------
62 // Task Dispatcher hooks
63 // The following hooks are called by the task dispatcher.
64 //-----------------------------------------------------------------------------
65
66 void TD_Init(void) // Called once at startup
67 {
68 1 Rwuen = TRUE; // Enable remote-wakeup
69 1 CPUCS = 0x10; // CLKSPD[1:0]=10, for 48MHz operation
70 1 // CLKOE=0, don't drive CLKOUT
71 1 GpifInit( ); // init GPIF engine via GPIFTool output file
72 1
73 1 // Registers which require a synchronization delay, see section 15.14
74 1 // FIFORESET FIFOPINPOLAR
75 1 // INPKTEND OUTPKTEND
76 1 // EPxBCH:L REVCTL
77 1 // GPIFTCB3 GPIFTCB2
78 1 // GPIFTCB1 GPIFTCB0
79 1 // EPxFIFOPFH:L EPxAUTOINLENH:L
80 1 // EPxFIFOCFG EPxGPIFFLGSEL
81 1 // PINFLAGSxx EPxFIFOIRQ
82 1 // EPxFIFOIE GPIFIRQ
83 1 // GPIFIE GPIFADRH:L
84 1 // UDMACRCH:L EPxGPIFTRIG
85 1 // GPIFTRIG
86 1
87 1 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
88 1 // ...these have been replaced by GPIFTC[B3:B0] registers
89 1
90 1 SYNCDELAY;
91 1 // REVCTL = 0x01; // use enhanced packet handling
92 1 REVCTL = 0x03; //SET DYN_OUT=1,ENH_PKT=1
93 1 /* // EP1OUT BULK 00100000B
94 1 SYNCDELAY; // see TRM section 15.14
95 1 EP1OUTCFG = 0x20; // clear valid bit
96 1
97 1 // EP1IN BULK 00100000B
98 1 SYNCDELAY;
99 1 EP1INCFG = 0x20; // clear valid bit
100 1 */
101 1 // EP2 512 BULK OUT 4x 10100000B
102 1 SYNCDELAY; // see TRM section 15.14
103 1 // EP2CFG = 0xA0; // BUF[1:0]=00 for 4x buffering
104 1 EP2CFG = 0xA2; // BUF[1:0]=00 for 2x buffering
105 1 // EP6 512 BULK IN 4x 11100000B
106 1 SYNCDELAY; //
107 1 //EP6CFG = 0xE0; // BUF[1:0]=00 for 4x buffering
108 1 EP6CFG = 0xE2; // BUF[1:0]=00 for 2x buffering
109 1 //10.06
110 1 // EP4 and EP8 are not used in this implementation...
111 1 SYNCDELAY; //
112 1 EP4CFG = 0x20; // clear valid bit
113 1 SYNCDELAY; //
114 1 EP8CFG = 0x60; // clear valid bit
115 1
116 1 SYNCDELAY; //
117 1 FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
C51 COMPILER V6.23a PERIPH 10/26/2005 19:02:17 PAGE 3
118 1 SYNCDELAY; //
119 1 FIFORESET = 0x02; // reset, FIFO 2
120 1 SYNCDELAY; //
121 1 FIFORESET = 0x04; // reset, FIFO 4
122 1 SYNCDELAY; //
123 1 FIFORESET = 0x06; // reset, FIFO 6
124 1 SYNCDELAY; //
125 1 FIFORESET = 0x08; // reset, FIFO 8
126 1 SYNCDELAY; //
127 1 FIFORESET = 0x00; // deactivate NAK-ALL to restore normal operation
128 1
129 1 // 8-bit bus (WORDWIDE=0)...
130 1 /*
131 1 SYNCDELAY; //
132 1 EP2FIFOCFG = 0x10; //AUTOOUT=1,WORDWIDE=0,ZEROLENIN=0
133 1 SYNCDELAY; //
134 1 EP6FIFOCFG = 0x08; //AUTOIN=1,WORDWIDE=0,ZEROLENIN=0
135 1 */
136 1 SYNCDELAY; //
137 1 EP2FIFOCFG = 0x00;
138 1 // EP2FIFOCFG = 0x10; // EP2 is AUTOOUT=1, AUTOIN=0, ZEROLEN=0, WORDWIDE=0
139 1 SYNCDELAY; //
140 1 EP6FIFOCFG = 0x00;
141 1
142 1 //OUT endpoints do NOT come up armed
143 1 // SYNCDELAY;
144 1 // EP2BCL = 0x80; // arm first buffer by writing BC w/skip=1
145 1 // SYNCDELAY;
146 1 // EP2BCL = 0x80; // arm second buffer by writing BC w/skip=1
147 1
148 1 SYNCDELAY;
149 1 OUTPKTEND = 0x82; //ARM QUAD EP2 BUFFERS TO "PRIME THE PUMP"
150 1 SYNCDELAY;
151 1 OUTPKTEND = 0x82;
152 1 SYNCDELAY;
153 1 // OUTPKTEND = 0x82;
154 1 // SYNCDELAY;
155 1 // OUTPKTEND = 0x82;
156 1 // SYNCDELAY; //
157 1 /*
158 1 SYNCDELAY;
159 1 EP6AUTOINLENH = 0x02; //if AUTOIN=1,auto commit 512 byte packets
160 1 SYNCDELAY;
161 1 EP6AUTOINLENL = 0x00;
162 1 */
163 1 // “all” EP2 buffers automatically arm when AUTOOUT
164 1 // OUT endp's come up "unarmed" in the cpu domain
165 1 // ...to "arm" the endp's when AUTOOUT=0 the cpu write's xBCL w/skip=1 (N times)
166 1
167 1 // IN endp's come up in the cpu/peripheral domain
168 1
169 1 // setup INT4 as internal source for GPIF interrupts
170 1 // using INT4CLR (SFR), automatically enabled
171 1 /* INTSETUP |= 0x0B; // Enable INT4 FIFO/GPIF Autovectoring,Enable INT2
172 1 SYNCDELAY; // used here as "delay"
173 1 EXIF &= ~0x40; // just in case one was pending...CLEAR INT2,INT4
174 1 SYNCDELAY; // used here as "delay"
175 1 GPIFIRQ = 0x02; //GPIFWF=1,GPIFDONE=0
176 1 SYNCDELAY; //
177 1 GPIFIE = 0x02; // Enable GPIFWF interrupt
178 1 SYNCDELAY; //
179 1 EIE |= 0x05; // Enable INT4 ISR, EIE.2(EIEX4=1),Enable INT2
C51 COMPILER V6.23a PERIPH 10/26/2005 19:02:17 PAGE 4
180 1 SYNCDELAY;
181 1 EPIE |= 0x10; //Enable ep2 ISR
182 1
183 1 INTSETUP |= 0x03; // Enable INT4 FIFO/GPIF Autovectoring
184 1 SYNCDELAY; // used here as "delay"
185 1 EXIF &= ~0x40; // just in case one was pending...
186 1 SYNCDELAY; // used here as "delay"
187 1 GPIFIRQ = 0x02;
188 1 SYNCDELAY; //
189 1 GPIFIE = 0x02; // Enable GPIFWF interrupt
190 1 SYNCDELAY; //
191 1 EIE |= 0x04; // Enable INT4 ISR, EIE.2(EIEX4=1)
192 1 */
193 1 // NAKIRQ |= ~bmIBN; // clear any pending PING-NAK IRQ
194 1 // NAKIE |= bmEP2PING; // enable the PING-NAK interrupt for EP2 and EP4
195 1
196 1 // ALREADY_READ = TRUE;
197 1 Flag_Of_Command = FALSE; //no command
198 1 // CmdAddress = CMDADDR; //command address initialed
199 1 Flag_Of_DataHI = TRUE; //data lies in high area
200 1 // Flag_Of_DataHI = FALSE; //data lies in LOW area
201 1 // FIRSTENTRY = TRUE;
202 1 // setup GPIF transaction count
203 1 SYNCDELAY;
204 1 GPIFTCB3 = 0x00;
205 1 SYNCDELAY;
206 1 GPIFTCB2 = 0x00;
207 1 SYNCDELAY;
208 1 GPIFTCB1 = 0x00;
209 1 SYNCDELAY;
210 1 GPIFTCB0 = 0x00;
211 1
212 1 PORTACFG = 0;
213 1 OEA = 0xFF; //USE PA.7 WHEN DEBUG
214 1
215 1 IOA = 0; //PA.7=1
216 1 COUNT = 0;
217 1 cishu = 0;
218 1 }
219 // EP2468STAT
220 // b7 b6 b5 b4 b3 b2 b1 b0
221 // EP8F EP8E EP6F EP6E EP4F EP4E EP2F EP2E
222
223 void TD_Poll(void) // Called repeatedly while the device is idle
224 {
225 1 // WORD DatAddress; //data address 10.06
226 1 // static WORD xFIFOTC_OUT = 0x0000;
227 1 // CmdAddress = CMDADDR; //command address initialed
228 1 // IOA = 0;
229 1 // is the host sending data...
230 1 if( !( EP2468STAT & 0x01 ) )
231 1 {
232 2 // IOA = 0x01;
233 2 // EP2EF=0, when endp buffer "not" empty
234 2
235 2 // ...at this point the pkt. switched from the usb domain to the cpu domain
236 2
237 2 // if the host sent a pkt... then a buffer was available
238 2 // AUTOOUT=0, so pass pkt. to peripheral domain - (GPIF)
239 2 SYNCDELAY;
240 2 OUTPKTEND = 0x02; // w/skip=0
241 2 SYNCDELAY;
C51 COMPILER V6.23a PERIPH 10/26/2005 19:02:17 PAGE 5
242 2 // IOA = 0;
243 2 // EP2BCL = 0x80; // arm buffer by writing BC w/skip=1
244 2 // SYNCDELAY;
245 2 }
246 1 /* if( !( EP24FIFOFLGS & 0x02 ) )
247 1 { // EP2EF=0 when FIFO “not” empty, host sent pkt.
248 1 SYNCDELAY;
249 1 OUTPKTEND = 0x02; // SKIP=0, pass buffer on to master
250 1 SYNCDELAY;
251 1 }*/
252 1 // else
253 1 // {
254 1 // host is "not" sending data...
255 1 // }
256 1 // is the peripheral interface idle...
257 1 if( GPIFTRIG & 0x80 )
258 1 {
259 2 // DONE=1, when GPIF is "idle"
260 2
261 2 // check if there's a pkt in the peripheral domain...
262 2 if( EP24FIFOFLGS & 0x02 )
263 2 {
264 3 // ...EF=1 when buffer "empty", no more data to xfr. //
265 3 }
266 2 else
267 2 {
268 3 // IOA = 0x01;
269 3 // EF=0, when slave fifo is "not empty"
270 3 // ...the cpu passed the pkt. to the peripheral domain
271 3 // SYNCDELAY;
272 3 // OUTPKTEND = 0x02; // SKIP=0, pass buffer on to master
273 3 // SYNCDELAY;
274 3 // peripheral ALWAYS "not full"...
275 3 SYNCDELAY;
276 3 GPIFWFSELECT = 0xE4; //INITIAL WAVEFORM added at 10.06
277 3 Peripheral_SetAddress( CMDADDR );
278 3 // xFIFOTC_OUT = ( ( EP2FIFOBCH << 8 ) + EP2FIFOBCL );
279 3
280 3 // setup GPIF transaction count
281 3 SYNCDELAY;
282 3 EP2GPIFTCH = EP2FIFOBCH;
283 3 SYNCDELAY;
284 3 EP2GPIFTCL = EP2FIFOBCL;
285 3
286 3
287 3 // trigger FIFO write transaction(s), using SFR
288 3 // R/W=0, EP[1:0]=00 for EP2 write(s)
289 3 SYNCDELAY;
290 3 GPIFTRIG = GPIF_EP2;
291 3
292 3 // NOTE: 512 bytes transfers in ~75usec on 8-bit async bus
293 3 // ...once master (GPIF) drains OUT pkt, it (re)arms to usb domain
294 3
295 3 // if( xFIFOTC_OUT < 512 )
296 3 // {
297 3 // handle short pkt. to peripheral
298 3
299 3 // wait for the transaction to terminate naturally...
300 3 SYNCDELAY;
301 3 while( !( GPIFTRIG & 0x80 ) )
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