nvidia_vid.c

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/*
   nvidia_vid - VIDIX based video driver for NVIDIA chips
   Copyrights 2003 - 2004 Sascha Sommer. This file is based on sources from
   RIVATV (rivatv.sf.net)
   Licence: GPL
   WARNING: THIS DRIVER IS IN BETA STAGE
   
   multi buffer support and TNT2 fixes by Dmitry Baryshkov
*/


#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <unistd.h>


#include "vidix.h"
#include "fourcc.h"
#include "libdha.h"
#include "pci_ids.h"
#include "pci_names.h"
#include "bswap.h"


pciinfo_t pci_info;


#define MAX_FRAMES 3
#define NV04_BES_SIZE 1024*2000*4


static vidix_capability_t nvidia_cap = {
    "NVIDIA RIVA OVERLAY DRIVER",
    "Sascha Sommer <[e-mail]>",
    TYPE_OUTPUT,
    { 0, 0, 0, 0 },
    2046,
    2046,
    4,
    4,
    -1,
    FLAG_UPSCALER|FLAG_DOWNSCALER,
    VENDOR_NVIDIA2,
    -1,
    { 0, 0, 0, 0 }
};


unsigned int vixGetVersion(void){
    return(VIDIX_VERSION);
}


#define NV_ARCH_03  0x03
#define NV_ARCH_04  0x04
#define NV_ARCH_10  0x10
#define NV_ARCH_20  0x20
#define NV_ARCH_30  0x30

struct nvidia_cards {
  unsigned short chip_id;
  unsigned short arch;
};

static struct nvidia_cards nvidia_card_ids[] = {
  /*NV03*/
  {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03},
  {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03},
  /*NV04*/
  {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04},
  {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04},  
  {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04},  
  {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04},  
  {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04},
  {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04},
  {DEVICE_NVIDIA2_TNT,NV_ARCH_04},
  {DEVICE_NVIDIA2_TNT2,NV_ARCH_04},  
  {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04},  
  {DEVICE_NVIDIA2_UTNT2	,NV_ARCH_04},
  {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04},
  {DEVICE_NVIDIA_NV5_ALADDIN_TNT2,NV_ARCH_30},
  /*NV10*/
  {DEVICE_NVIDIA_NV18_GEFORCE_PCX,NV_ARCH_10},
  {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10},
  {DEVICE_NVIDIA_NV10DDR_GEFORCE_256,NV_ARCH_10},
  {DEVICE_NVIDIA_NV10GL_QUADRO,NV_ARCH_10},
  {DEVICE_NVIDIA_NV11_GEFORCE2_MX_MX,NV_ARCH_10},
  {DEVICE_NVIDIA_NV11DDR_GEFORCE2_MX,NV_ARCH_10},
  {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10},
  {DEVICE_NVIDIA_NV11GL_QUADRO2_MXR_EX,NV_ARCH_10},
  {DEVICE_NVIDIA_NV15_GEFORCE2_GTS_PRO,NV_ARCH_10},
  {DEVICE_NVIDIA_NV15DDR_GEFORCE2_TI,NV_ARCH_10},
  {DEVICE_NVIDIA_NV15BR_GEFORCE2_ULTRA,NV_ARCH_10},
  {DEVICE_NVIDIA_NV15GL_QUADRO2_PRO,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17_GEFORCE4_MX,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17_GEFORCE4_MX2,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17_GEFORCE4_MX3,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17_GEFORCE4_MX4,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17GL_QUADRO4_550,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17_GEFORCE4_4402,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17GL_QUADRO4_200_400,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17GL_QUADRO4_5502,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17GL_QUADRO4_5503,NV_ARCH_10},
  {DEVICE_NVIDIA_NV17_GEFORCE4_410,NV_ARCH_10},
  {DEVICE_NVIDIA_NV18_GEFORCE4_MX,NV_ARCH_10},
  {DEVICE_NVIDIA_NV18_GEFORCE4_MX2,NV_ARCH_10},
  {DEVICE_NVIDIA_NV18_GEFORCE4_MX3,NV_ARCH_10},
  {DEVICE_NVIDIA_NV18_GEFORCE4_MX4,NV_ARCH_10},
  {DEVICE_NVIDIA_NV18M_GEFORCE4_448,NV_ARCH_10},
  {DEVICE_NVIDIA_NV18M_GEFORCE4_488,NV_ARCH_10},
  {DEVICE_NVIDIA_NV18GL_QUADRO4_580,NV_ARCH_10},
  {DEVICE_NVIDIA_NV18GL_QUADRO4_NVS,NV_ARCH_10},
  {DEVICE_NVIDIA_NV18GL_QUADRO4_380,NV_ARCH_10},
  {DEVICE_NVIDIA_NV18M_GEFORCE4_4482,NV_ARCH_10},
  {DEVICE_NVIDIA_NVCRUSH11_GEFORCE2_MX,NV_ARCH_10},
  {DEVICE_NVIDIA_NFORCE2_AGP_DIFFERENT,NV_ARCH_10},
  {DEVICE_NVIDIA_NFORCE2_AGP,NV_ARCH_10},
  {DEVICE_NVIDIA_NV18_GEFORCE4_MX5,NV_ARCH_10},
  /*NV20*/
  {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20},
  {DEVICE_NVIDIA_NV20_GEFORCE3_TI,NV_ARCH_20},
  {DEVICE_NVIDIA_NV20_GEFORCE3_TI2,NV_ARCH_20},
  {DEVICE_NVIDIA_NV20DCC_QUADRO_DCC,NV_ARCH_20},
  {DEVICE_NVIDIA_NV25_GEFORCE4_TI,NV_ARCH_20},
  {DEVICE_NVIDIA_NV25_GEFORCE4_TI2,NV_ARCH_20},
  {DEVICE_NVIDIA_NV25_GEFORCE4_TI3,NV_ARCH_20},
  {DEVICE_NVIDIA_NV25_GEFORCE4_TI4,NV_ARCH_20},
  {DEVICE_NVIDIA_NV25GL_QUADRO4_900,NV_ARCH_20},
  {DEVICE_NVIDIA_NV25GL_QUADRO4_750,NV_ARCH_20},
  {DEVICE_NVIDIA_NV25GL_QUADRO4_700,NV_ARCH_20},
  {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20},
  {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20},
  {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20},
  {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20},
  {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20},
  {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20},
  {DEVICE_NVIDIA_NV28GLM_QUADRO4_700,NV_ARCH_20},
  /*NV30*/
  {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30},
  {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30},
  {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30},
  {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30},
  {DEVICE_NVIDIA_NV31,NV_ARCH_30},
  {DEVICE_NVIDIA_NV31_GEFORCE_FX3,NV_ARCH_30},
  {DEVICE_NVIDIA_NV312,NV_ARCH_30},
  {DEVICE_NVIDIA_NV313,NV_ARCH_30},
  {DEVICE_NVIDIA_NV31M_GEFORCE_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV31M_GEFORCE_FX2,NV_ARCH_30},
  {DEVICE_NVIDIA_NVIDIA_QUADRO_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV314,NV_ARCH_30},
  {DEVICE_NVIDIA_NV315,NV_ARCH_30},
  {DEVICE_NVIDIA_NV316,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34_GEFORCE_FX4,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34M_GEFORCE_FX2,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34_GEFORCE_FX5,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34_GEFORCE_FX6,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34M_GEFORCE_FX3,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34M_GEFORCE_FX4,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34GL_QUADRO_NVS,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34GLM_GEFORCE_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34_GEFORCE_FX7,NV_ARCH_30},
  {DEVICE_NVIDIA_NV34,NV_ARCH_30},
  {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30},
  {DEVICE_NVIDIA_NV35_GEFORCE_FX3,NV_ARCH_30},
  {DEVICE_NVIDIA_NV38_GEFORCE_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV35_GEFORCE_FX4,NV_ARCH_30},
  {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV35GL_QUADRO_FX2,NV_ARCH_30},
  {DEVICE_NVIDIA_NV36_1_GEFORCE_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV36_2_GEFORCE_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV36_GEFORCE_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV36_4_GEFORCE_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV36_5,NV_ARCH_30},
  {DEVICE_NVIDIA_NV36_GEFORCE_FX2,NV_ARCH_30},
  {DEVICE_NVIDIA_NV36_GEFORCE_FX3,NV_ARCH_30},
  {DEVICE_NVIDIA_NV36,NV_ARCH_30},
  {DEVICE_NVIDIA_NV362,NV_ARCH_30},
  {DEVICE_NVIDIA_NV36_QUADRO_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV36GL_QUADRO_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV36GL,NV_ARCH_30},
  {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV37GL_QUADRO_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV37GL_QUADRO_FX2,NV_ARCH_30},
  {DEVICE_NVIDIA_NV38GL_QUADRO_FX,NV_ARCH_30},
  /* FIXME are they different? */
  {DEVICE_NVIDIA_NV40_GEFORCE_6800,NV_ARCH_30},
  {DEVICE_NVIDIA_NV40_GEFORCE_68002,NV_ARCH_30},
  {DEVICE_NVIDIA_NV40_2,NV_ARCH_30},
  {DEVICE_NVIDIA_NV40_3,NV_ARCH_30},
  {DEVICE_NVIDIA_NV40_GEFORCE_68003,NV_ARCH_30},
  {DEVICE_NVIDIA_NV40GL,NV_ARCH_30},
  {DEVICE_NVIDIA_NV40GL_QUADRO_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV41_0,NV_ARCH_30},
  {DEVICE_NVIDIA_NV41_1,NV_ARCH_30},
  {DEVICE_NVIDIA_NV41_2,NV_ARCH_30},
  {DEVICE_NVIDIA_NV41_8,NV_ARCH_30},
  {DEVICE_NVIDIA_NV41GL,NV_ARCH_30},
  {DEVICE_NVIDIA_NV40_GEFORCE_6800_GEFORCE,NV_ARCH_30},
  {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE,NV_ARCH_30},
  {DEVICE_NVIDIA_NV43_GEFORCE_6600,NV_ARCH_30},
  {DEVICE_NVIDIA_NV45GL_QUADRO_FX,NV_ARCH_30},
  {DEVICE_NVIDIA_NV40_GEFORCE_68004,NV_ARCH_30}
};


static int find_chip(unsigned chip_id){
  unsigned i;
  for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++)
  {
    if(chip_id == nvidia_card_ids[i].chip_id)return i;
  }
  return -1;
}

int vixProbe(int verbose, int force){
    pciinfo_t lst[MAX_PCI_DEVICES];
    unsigned i,num_pci;
    int err;

    if (force)
	    printf("[nvidia_vid]: warning: forcing not supported yet!\n");
    err = pci_scan(lst,&num_pci);
    if(err){
	printf("[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err));
	return err;
    }
    else {
	err = ENXIO;
	for(i=0; i < num_pci; i++){
	    if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){
		int idx;
		const char *dname;
		idx = find_chip(lst[i].device);
		if(idx == -1)
		    continue;
		dname = pci_device_name(lst[i].vendor, lst[i].device);
		dname = dname ? dname : "Unknown chip";
		printf("[nvidia_vid] Found chip: %s\n", dname);
		nvidia_cap.device_id = lst[i].device;
		err = 0;
		memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
		break;
	    }
	}
    }
    if(err && verbose) printf("[nvidia_vid] Can't find chip\n");
    return err;
}




/*
 * PCI-Memory IO access macros.
 */
#define VID_WR08(p,i,val)  (((uint8_t *)(p))[(i)]=(val))
#define VID_RD08(p,i)	   (((uint8_t *)(p))[(i)])

#define VID_WR32(p,i,val)  (((uint32_t *)(p))[(i)/4]=(val))
#define VID_RD32(p,i)	   (((uint32_t *)(p))[(i)/4])

#ifndef USE_RMW_CYCLES
/*
 * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default.
 */

#define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory")

#undef	VID_WR08
#define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); })
#undef	VID_RD08
#define VID_RD08(p,i)     ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; })

#undef	VID_WR32
#define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); })
#undef	VID_RD32
#define VID_RD32(p,i)     ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; })
#endif /* USE_RMW_CYCLES */

#define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val))
#define VID_OR32(p,i,val)  VID_WR32(p,i,VID_RD32(p,i)|(val))
#define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val))






struct rivatv_chip {
	volatile uint32_t *PMC;	   /* general control			*/
	volatile uint32_t *PME;	   /* multimedia port			*/
	volatile uint32_t *PFB;	   /* framebuffer control		*/
	volatile uint32_t *PVIDEO; /* overlay control			*/
	volatile uint8_t *PCIO;	   /* SVGA (CRTC, ATTR) registers	*/
	volatile uint8_t *PVIO;	   /* SVGA (MISC, GRAPH, SEQ) registers */
	volatile uint32_t *PRAMIN; /* instance memory			*/
	volatile uint32_t *PRAMHT; /* hash table			*/
	volatile uint32_t *PRAMFC; /* fifo context table		*/
	volatile uint32_t *PRAMRO; /* fifo runout table			*/
	volatile uint32_t *PFIFO;  /* fifo control region		*/
	volatile uint32_t *FIFO;   /* fifo channels (USER)		*/
	volatile uint32_t *PGRAPH; /* graphics engine                   */

	unsigned long fbsize;		   /* framebuffer size		   */
	int arch;		   /* compatible NV_ARCH_XX define */
	int realarch;		   /* real architecture		   */
	void (* lock) (struct rivatv_chip *, int);
};
typedef struct rivatv_chip rivatv_chip;